A Scalable Architecture for MPEG-4 Wavelet Quantization

Wavelet-based image compression has been adopted in MPEG-4 for visual texture coding. All wavelet quantization schemes in MPEG-4—Single Quantization (SQ), Multiple Quantization (MQ) and Bi-level Quantization—use Embedded Zero Tree (EZT) coding followed by an adaptive arithmetic coder for the compression and quantization of a wavelet image. This paper presents the OZONE chip, a dedicated hardware coprocessor for EZT and arithmetic coding. Realized in a 0.5 m CMOS technology and operating at 32 MHz, the EZT coder is capable of processing up to 25.6 Mega pixel-bitplanes per second. This is equivalent to the lossless compression of 31.6 8-bit grayscale CIF images (352 × 288) per second. The adaptive arithmetic coder processes up to 10 Mbit per second. The combination of the performance of the EZT coder and the arithmetic coder allows the OZONE to perform visual-lossless compression of more than 30 CIF images per second. Due to its novel and scalable architecture, parallel operation of multiple OZONEs is supported. The OZONE functionality is demonstrated on a PC-based compression system.     

Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors

Upcoming multi-media compression applications will require high memory bandwidth. In this paper, we estimate that a software reference implementation of an MPEG-4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352×288) Video Object Plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance.However, we also show that we can heavily improve on the memory transfers, without sacrificing speed (even gaining about 10% on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have manually applied an extended version of our data transfer and storage exploration (DTSE) methodology, which was originally developed for custom hardware implementations.     

A Voltage and Frequency Droop Control Method for Parallel Inverters

In this paper, a new control method for the parallel operation of inverters operating in an island grid or connected to an infinite bus is described. Frequency and voltage control, including mitigation of voltage harmonics, are achieved without the need for any common control circuitry or communication between inverters. Each inverter supplies a current that is the result of the voltage difference between a reference ac voltage source and the grid voltage across a virtual complex impedance. The reference ac voltage source is synchronized with the grid, with a phase shift, depending on the difference between rated and actual grid frequency. A detailed analysis shows that this approach has a superior behavior compared to existing methods, regarding the mitigation of voltage harmonics, short-circuit behavior and the effectiveness of the frequency and voltage control, as it takes the R to X line impedance ratio into account. Experiments show the behavior of the method for an inverter feeding a highly nonlinear load and during the connection of two parallel inverters in operation.     

用FPGA实现高效分组处理

最近,我参加了斯坦福大学举办的一个非常有吸引力的Clean Slate因特网技术研讨会.研讨会的主题是重新创建因特网基础设施,以解决现有因特网的一些缺点,同时可以支持新的应用和服务.     

Analysis and experimental verification of digital substrate noisegeneration for epi-type substrates

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends     

Synthesis of pipelined DSP accelerators with dynamic scheduling

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis is put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology is illustrated by means of an image encoding filter bank     

CoWare—A design environment for heterogeneous hardware/software systems

This paper addresses CoWare: an environment for design of heterogeneous systems on chip. These systems are heterogeneous both in terms of specification and implementation. CoWare is based on a communicating processes data-model which supports encapsulation and refinement and makes a strict separation between functional and communication behaviour. Encapsulation enables the reuse of existing specification and design environments (languages, simulators, compilers). Refinement provides for a consistent and integrated path from specification to implementation. The design steps that will be addressed include: system specification, simulation at various abstraction levels, data path synthesis, communication refinement and hardware/software co-design. A spread-spectrum based pager system serves to illuminate the design process in the CoWare environment.     

Model-based generation of low distortion currents in grid-coupled PWM-inverters using an LCL output filter

In this paper, a single phase inductance-capacitance-inductance (LCL) output stage for grid coupled inverters is designed and built. An accurate model and observer of the output filter and the distorted grid voltage are implemented. The paper deals with the construction of a 14-state model, and the feedback control loop to obtain adequate closed loop response. Simulations indicate a good performance of the controller, with a total harmonic current distortion (THD) below 1%. Experimental results confirm simulations, and illustrate the correct operation of the Kalman observer to estimate the distorted grid voltage (THD 3%). The observer only uses the inverter current measurement as input. The output filter effectively reduces the pulsewidth modulation harmonics in the grid current.     

Single-package integration of RF blocks for a 5 GHz WLANapplication

Transceivers for future digital telecommunications applications (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. Today's single-chip solutions for RF front-ends do not yield complete system integration. For example, they typically still need external components for impedance matching, for antenna switches, for power amplifiers and for RF bandpass filters (BPFs). Furthermore, problems of substrate coupling (either manifesting as analog crosstalk or as noise coupling from the digital part to the analog part on mixed-signal chip) become more important with increasing integration. A system-in-a-package (SiP) approach can address these problems. High quality components can be integrated in the package, avoiding lower quality on-chip passives or circumventing expensive chip technology adaptations. Virtually all external components can be integrated, as shown in this paper for the case of the bandpass filters and the impedance matching. Even the antenna is a candidate for integration in the package. Further, a clever chip partitioning can reduce the substrate coupling problem. Partitioning also allows using the best IC-technoiogy for each component. This paper reports on a fully integrated single-package RF prototype module for a 5 GHz WLAN receiver front-end, which is intended to demonstrate the concept of SiP integration. The approach, that is illustrated here with prototype RF blocks for a 5 GHz WLAN application, is implemented with a thin film multichip module (MCM-D) interconnect technology. This technology also allows the integration of high quality passive components. With these passives, low-loss filters can be implemented. The use of passives, filters and off-the-shelf, active, bare die components opens the way to successful system integration