Design of High Speed AWGN Communication Channel Emulator

This paper presents a method for designing a high accuracy white gaussian noise generator suitable for communication channel emulation. The proposed solution is based on the combined use of the Box-Muller method and the central limit theorem. The resulting architecture provides a high accuracy AWGN with a low complexity architecture for a digital implementation in FPGA. The performance is studied by means of MATLAB simulations and various complexity figures are given.     

Quasi-Maximum-Likelihood Detector Based on Geometrical Diversification Greedy Intensification

This letter proposes a quasi optimum maximum likelihood detection technique based on Geometrical Diversification and Greedy Intensification (GDGI). The presented detector scheme is shown to achieve almost optimal performance for all signal-to-noise ratio (SNR) values and a cubic computation complexity in the problem dimension. It possesses a regular structure well suited for hardware implementation. Simulation results show that for a system with a high dimension of n = 60, the loss is approximately 0.35 dB at BER=10^-5 compared to an optimal decoding.     

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Journal of Signal Processing Systems - This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new...     

VLSI architectures for the MAP algorithm

This paper presents several techniques for the very large-scale integration (VLSI) implementation of the maximum a posteriori (MAP) algorithm. In general, knowledge about the implementation of the Viterbi (1967) algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the add-MAX* operation, which is the add-compare-select operation of the Viterbi algorithm with an added offset. We show that the critical path of the algorithm can be reduced if the add-MAX* operation is reordered into an offset-add-compare-select operation by adjusting the location of registers. A general scheduling for the MAP algorithm is presented which gives the tradeoffs between computational complexity, latency, and memory size. Some of these architectures eliminate the need for RAM blocks with unusual form factors or can replace the RAM with registers. These architectures are suited to VLSI implementation of turbo decoders.     

A VLSI decoder for a new type of constellations adapted to the Rayleigh Fading Channel

Diversity is the key solution to obtain efficient channel coding in wireless communications, where the signal is subject to fading (Rayleigh Fading Channel). For high spectral efficiency, the best solutions used nowadays are based on QAM constellations of 1-order diversity, associated with a binary code or a trellis coded modulation to increase the overall diversity. It has been shown that a new class of d-dimensional non-QAM constellations, named -constellations, can bring a d-order diversity without the addition of redundancy. Combined with classical coding techniques, -constellations are very efficient. However, the decoding algorithm is far more complicated for -constellations than for QAM-constellations. A sub-optimal algorithm that allows the decoding of -constellations is proposed. An example of an application for a 4 bits/Hz/s spectral efficiency with a 4-D -constellation is given. The VLSI architecture of the decoder is described. The implementation leads to 72 K gates, a binary rate of 32 Mbits/s and a BER of 10^-3 for a SNR of 14 dB.     

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of practical implementations: quantization and memory. Quantization can strongly degrade performance and memory area can constitute up to 70% of the total area of the decoder implementation. This is the case of the DVB-S2,-T2 and -C2 decoders when considering long frames. This paper is then dedicated to the optimization of these decoders. We first focus on the reduction of the number of quantization bits and propose solutions based on the efficient saturation of the channel values, the extrinsic messages and the a posteriori probabilities (APP). We reduce from 6 to 5 the number of quantization bits for the channel and the extrinsic messages and from 8 to 6 the APPs, without introducing any performance loss. We then consider the optimization of the size of the extrinsic memory considering a multiple code rates decoder. The paper finally presents an optimized fixed-point architecture of a DVB-S2 layered decoder and its implementation on an FPGA device.     

Comparison of the NIST and BIPM Medium-Energy X-Ray Air-Kerma Measurements

The air-kerma standards used for the measurement of medium-energy x rays were compared at the National Institute of Standards and Technology (NIST) and at the Bureau International des Poids et Mesures (BIPM). The comparison involved a series of measurements at the BIPM and the NIST using the air-kerma standards and two NIST reference-class transfer ionization standards. Reference beam qualities in the range from 60 kV to 300 kV were used. The results show the standards to be in agreement within the combined standard uncertainty of the comparison of 0.35 %.     

Generic Description and Synthesis of LDPC Decoders

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.     

Algebraic tools to build modulation schemes for fading channels

A unified framework is presented in order to build lattice constellations matched to both the Rayleigh fading channel and the Gaussian channel. The method encompasses the situations where the interleaving is done on the real components or on two-dimensional signals. In the latter case, a simple construction of lattices congruent to the densest binary lattices with respect to the Euclidean distance is proposed. It generalizes, in a sense to be clarified later, the structural construction proposed by Forney (1991). These constellations are next combined with coset codes. The partitioning rules and the gain formula are similar to those used for the Gaussian channel     

Decoding of constellations matched to the Rayleigh fading channel

It has recently been shown that a new class of d-dimensional non-QAM constellations matched for the Rayleigh fading channel (π-constellations), allows a d-order diversity without addition of redundancy [6–8]. Combined with traditional coding techniques, π-constellations are very efficient. However, the decoding algorithm of these constellations is far more complicated than that for qam-constellations. A sub-optimal algorithm for the decoding of π-constellations is proposed in this work. An example of application for 4 bit/Hz.s spectral efficiency with a 4-D π-constellations is given and the VLSI architecture of the decoder is described. The implementation, in a 0.8 μm standard cell technology, can be achieved with a 72 K gate circuit, with a binary rate of 32 Mbit/s and, from simulation, a binary error rate of 10^{- 3} for a snr of 14 dB.