Dual Adaptive Dynamic Control of Mobile Robots Using Neural Networks

This paper proposes two novel dual adaptive neural control schemes for the dynamic control of nonholonomic mobile robots. The two schemes are developed in discrete time, and the robot's nonlinear dynamic functions are assumed to be unknown. Gaussian radial basis function and sigmoidal multilayer perceptron neural networks are used for function approximation. In each scheme, the unknown network parameters are estimated stochastically in real time, and no preliminary offline neural network training is used. In contrast to other adaptive techniques hitherto proposed in the literature on mobile robots, the dual control laws presented in this paper do not rely on the heuristic certainty equivalence property but account for the uncertainty in the estimates. This results in a major improvement in tracking performance, despite the plant uncertainty and unmodeled dynamics. Monte Carlo simulation and statistical hypothesis testing are used to illustrate the effectiveness of the two proposed stochastic controllers as applied to the trajectory-tracking problem of a differentially driven wheeled mobile robot.     

A reconfigurable VLSI coprocessing system for the block matchingalgorithm

Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor custom VLSI design was implemented in 0.6 μm CMOS on a 4.12 min×2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search application, a sample system consisting of four coprocessors interfaced through a 33 MHz PCI bus will provide a speedup of 320× over an 80486 DX2/66 MHz and 64× over a 150-MHz Pentium running fully optimized assembly code     

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

A dual 10-b/200-MSPS pipelined digital-to-analog converter (DAC) suitable for communication applications is here presented. Prior implementation limitations have been overcome through circuit techniques. A prototype has been designed using a 4-metal-levels 3.3-V 0.5-/spl mu/m BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay-locked loop (DLL). The DAC shows 9.7 effective bits and 70 dB of spurious free dynamic range for a synthesized sine wave of 2 V/sub pp/ at 34 MHz and output rate of 200 MSPS. Altogether, the two DACs, their reference, and the DLL occupy an active area of 2.28 mm/sup 2/ and consume 693 mW at full speed.     

Frame Rate vs Resolution: A Subjective Evaluation of Spatiotemporal Perceived Quality Under Varying Computational Budgets

Maximizing performance for rendered content requires making compromises on quality parameters depending on the computational resources available . Yet, it is currently unclear which parameters best maximize perceived quality. This work investigates perceived quality across computational budgets for the primary spatiotemporal parameters of resolution and frame rate. Three experiments are conducted. Experiment 1 (n = 26) shows that participants prefer fixed frame rates of 60 frames per second (fps) at lower resolutions over 30 fps at higher resolutions. Experiment 2 (n = 24) explores the relationship further with more budgets and quality settings and again finds 60 fps is generally preferred even when more resources are available. Experiment 3 (n = 25) permits the use of adaptive frame rates, and analyses the resource allocation across seven budgets. Results show that while participants allocate more resources to frame rate at lower budgets the situation reverses once higher budgets are available and a frame rate of around 40 fps is achieved. In the overall, the results demonstrate a complex relationship between frame rate and resolution's effects on perceived quality. This relationship can be harnessed, via the results and models presented, to obtain more cost‐effective virtual experiences.     

A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed     

A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm×3.44 mm in a 0.35-μm CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s     

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% in the BI test time when using the proposed adaptive techniques.