Effect of gate poly-silicon depletion on MOSFET input impedance

One of the most challenging problems encountered in developing RF circuits is accurate prediction of MOS behavior at microwave signal and data frequencies. An attempt is made in this work to accurately model the device input impedance for the 1-20-GHz frequency range. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 0.11-/spl mu/m and 0.18-/spl mu/m technologies. The measured data illustrates that the device input impedance has a nonlinear frequency dependency. It is also shown that this variation in input impedance is a result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region.     

Longitudinal recording in a stray field

We have studied the sensitivity of soft error rate (SER) to an external magnetic field in longitudinal hard disk drives. We found that during writing SER is generally quadratic with field amplitude and symmetric with field direction. The application of an external field during writing also shifts the center of the track. In contrast, during reading SER is predominantly linear with field amplitude and antisymmetric with field direction. There is no shift in the track center when the field is applied during reading up to 100 Oe. We explain the difference in the track center shift between writing and reading in terms of the effect of the stray field on the servo positioning system.     

A VLSI design methodology for distributed arithmetic

Real-time signal processing requires fast computation of inner products. Distributed arithmetic is a method of inner product computation that uses table-lookup and addition in place of multiplication. Distributed arithmetic has previously been shown to produce novel and seemingly efficient architectures for a variety of signal processing computations; however the methods of design, analysis and comparison have been ad hoc. We propose a systematic method for synthesizing optimal VLSI architectures using distributed arithmetic.A partition of the inner product computation at the word and bit level produces a computation consisting of lookups and additions. We study two classes of algorithms to implement this computation, regular iterative algorithms and tree algorithms, each of which can be expressed in the form of a dependency graph. We use linear and nonlinear maps to assign computations to processors in space and time. Expressions are developed for the area, latency, period and arithmetic error for a particular partition and space/time map of the dependecy graph. We use these expressions to formulate a constrained optimization problem over a large class of architectures. We compare distributed arithmetic with more conventional methods for inner product computation and show how area, latency and period may be traded off while maintaining constant error.This work was supported by Ball Aerospace, Boulder, CO and by the Office of Naval Research, Electronics Branch, Arlington, VA under contract ONR 89-J-1070.     

Effects of decisional control and work orientation on persistence in preventive health behavior.

Examined persistence in the daily use of fluoride mouthrinse in 242 7th-graders from 3 inner-city and 2 suburban schools, as a function of an induced-choice manipulation concerning self-management strategies and freedom to participate in the program. Ss were assigned to either high- or low-choice decisional control manipulations. Ss' daily, home use of fluoride was monitored over 20 wks. To ameliorate the relatively lower persistence rates found previously among suburban vs urban Ss (A. K. Lund and S. S. Kegeles; see record 1988-11515-001), all Ss were given self-management and action instructions. Suburban Ss still declined in persistence relative to urban Ss. Females who received high choice persisted at a higher rate than girls who received low choice. Boys were unaffected by the manipulation. Ss' self-reported work orientation was positively associated with persistence. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling     

VLSI array algorithms and architectures for RSA modularmultiplication

We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are designed for Rivest-Shamir-Adelman (RSA) cryptography and are based on the familiar iterative Horner's rule, but use precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Both algorithms use a carry save adder scheme with module reduction performed on each intermediate partial product which results in an output in carry-save format. Regularity and local connections make both algorithms suitable for high-performance array implementation in FPGA's or deep submicron VLSI. The processing nodes consist of just one or two full adders and a simple multiplexor. The stored complement numbers need to be precalculated only when the modulus is changed, thus not affecting the performance of the main computation. In both cases, there exists a bit-level systolic schedule, which means the array can be fully pipelined for high performance and can also easily be mapped to linear arrays for various space/time tradeoffs     

Analog VLSI for robot path planning

Analog VLSI provides a convenient and high-performance engine for robot path planning. Laplace's equation is a useful formulation of the path-planning problem; however, digital solutions are very expensive. Since high precision is not required, an analog approach is attractive. A resistive network can be used to model the robot's domain with various boundary conditions for the source, target, and obstacles. A gradient descent can then be traced through the network by comparing node voltages. We built two analog CMOS VLSI chips to investigate the feasibility of this technique. Design issues included the choice of resistive element, tessellation of the domain, programming of the network, and readout of the settled network. Both chips can be connected to a standard VME bus interface to permit their use as coprocessors in otherwise digital systems.A preliminary short version of this paper was presented at the 1992 ASILOMAR Conf. on Computers, Signals and Systems.