Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO₂ dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance     

Parameters extraction of hafnium based gate oxide capacitors

From quantum simulations of both capacitance and current measurements, the main physical parameters (dielectric thickness and permittivity, doping levels) of hafnium based (HfSiO_x and HfO₂) gate oxide capacitors have been extracted. Three kinds of gates (n⁺-polysilicon, totally silicided (TOSI) NiSi and metal TiN gates) have been studied. In the case of thick (EOT between 11.1 and 12.3 nm) HfSiO_x gate oxides or thin (EOT inferior to 2 nm) HfO₂ stacks with n⁺-polysilicon or TiN gates, a good agreement between simulations and experimental data is obtained. Electron tunneling currents are prevalent in these stacks except for the specific case of TiN/HfO₂ stacks in p-substrate accumulation mode. In this case, electron and hole tunneling transparencies become of the same order of magnitude. Hole transport contribution can no more be neglected and should be taken into account in simulations.     

A three charge-states model for silicon nanocrystals nonvolatile memories

In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the continuous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/substrate interface, inside the SiO/sub 2/. This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena.     

Peculiarities of electron tunnel injection to the drain of EEPROMs

A specific time-resolved dynamic current measurement procedure is used to characterize high-field electron tunnel injection to the drain of EEPROMs. This allows the direct observation of a transient regime eventually occurring in the case of moderately doped drain. Another peculiarity is also evidenced, namely a stationary regime where measured current is far higher than anticipated by simulation. This is attributed to a non-equilibrium charge versus band-bending in the drain which is controlled by electron–hole pairs subsequent to impact ionization of electrons tunnelling from the gate.