Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

Detecting similarities in virtual machine behavior for cloud monitoring using smoothed histograms

The growing size and complexity of cloud systems determine scalability issues for resource monitoring and management. While most existing solutions consider each Virtual Machine (VM) as a black box with independent characteristics, we embrace a new perspective where VMs with similar behaviors in terms of resource usage are clustered together. We argue that this new approach has the potential to address scalability issues in cloud monitoring and management. In this paper, we propose a technique to cluster VMs starting from the usage of multiple resources, assuming no knowledge of the services executed on them. This innovative technique models VMs behavior exploiting the probability histogram of their resources usage, and performs smoothing-based noise reduction and selection of the most relevant information to consider for the clustering process. Through extensive evaluation, we show that our proposal achieves high and stable performance in terms of automatic VM clustering, and can reduce the monitoring requirements of cloud systems.     

Conceptual aspects of geometric quantum computation

Geometric quantum computation is the idea that geometric phases can be used to implement quantum gates, i.e., the basic elements of the Boolean network that forms a quantum computer. Although originally thought to be limited to adiabatic evolution, controlled by slowly changing parameters, this form of quantum computation can as well be realized at high speed by using nonadiabatic schemes. Recent advances in quantum gate technology have allowed for experimental demonstrations of different types of geometric gates in adiabatic and nonadiabatic evolution. Here, we address some conceptual issues that arise in the realizations of geometric gates. We examine the appearance of dynamical phases in quantum evolution and point out that not all dynamical phases need to be compensated for in geometric quantum computation. We delineate the relation between Abelian and non-Abelian geometric gates and find an explicit physical example where the two types of gates coincide. We identify differences and similarities between adiabatic and nonadiabatic realizations of quantum computation based on non-Abelian geometric phases.     

Light emission in AlGaAs/GaAs HEMTs and GaAs MESFETs induced by hotcarriers

Light emission in submicrometer gate AlGaAs/GaAs HEMTs and GaAs MESFETs has been observed at high drain bias values (>4.0 V). The spectral distribution of the emitted photons in the 1.7-2.9-eV range does not correspond to a simple Maxwellian distribution function of the electron energies in the channel. Light emission is observed in correspondence with nonnegligible gate and substrate hole currents, due to the collection of holes generated by impact ionization     

Hot electron effects on Al0.25Ga0.75As/GaAspower HFET's under off-state and on-state electrical stress conditions

This work shows a detailed comparison of the degradation modes caused by off-state and on-state room temperature electrical stress on the DC characteristics of power AlGaAs/GaAs heterostructure field effect transistors (HFET's) for X- and Ku-band applications. The devices are stressed under DC bias conditions that result in electron heating and impact ionization in the gate-drain region. Incremental stress experiments carried out at gate-drain reverse currents up to 3.3 mA/mm (for a total of more than 700 h) show a remarkably larger degradation for the off state stress, due to more pronounced electron heating at any fixed value of gate reverse current. This represents an important piece of information for the reliability engineer when it comes to designing the accelerated stress experiments for hot electron robustness evaluation. The degradation modes observed, all of a permanent nature, include threshold voltage and drain resistance increase and drain current and transconductance reduction     

Reliability evaluation of plastic packaged devices for long life applications by THB test

The reliability of transistors, bipolar and CMOS integrated circuits encapsulated in different types of plastic packages was investigated by using the 85°C/85% R.H. test with applied bias and the results compared with a long term operating life test. Particular attention was devoted to pointing out the influence of technology, process control and working conditions on device reliability and failure mechanisms.In micropackaged transistors the importance of surface passivation in protecting the devices against gold corrosion was forcused, while the need of good process control was confirmed by the results of the test on micropackaged linear integrated circuits.In dual-in-line CMOS integrated circuits silicon nitride and polymide give, in general, a superior protection, but good results were obtained also with normal P-glass passivation when a clever arrangement of layout design rules was adopted. Results obtained exhibit a significant improvement in the reliability of plastic packaged devices, with the best figures showing no failures after 15,000 hours at 85°C/85% R.H. test with bias.     

Thermally induced parasitic ungated FET in power MESFETs

The onset of a parasitic FET between the gate and the source (drain) has been observed by monitoring the reverse gate diode I−V characteristics of power GaAs MESFETs, subjected to accelerated aging tests. Such anomalous characteristics are attributed to localized microreactions at the gate metal-GaAs interface, which can be preferential sites for the occurrence of burn-out phenomena.     

Experimental and Monte Carlo analysis of impact-ionization inAlGaAs/GaAs HBT's

We present a detailed experimental and theoretical investigation of hot electron effects occurring in AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's) operating at low current densities. Electrons heated by the strong electric field at the base-collector junction give rise to impact ionization and light emission. A new general purpose weighted Monte Carlo procedure has been developed to study such effects. The importance of dead-space effects on the multiplication factor of the device is demonstrated. Good agreement is found between theory and experiment     

Prediction of impact-ionization-induced snap-back in advanced Sin-p-n BJT's by means of a nonlocal analytical model for the avalanchemultiplication factor

The authors point out that when a triangular shape for the electric field in the base-collector space-charge region of an n-p-n Si BJT (bipolar junction transistor) is assumed, the electron mean energy can be calculated analytically from a simplified energy-balance equation. On this basis a nonlocal-impact-ionization model, suitable for computer-aided circuit simulation, has been obtained and used to calculate the output characteristics at constant emitter-base voltage (grounded base) of advanced devices. Provided the experimental bias-dependent value of the base parasitic resistance is accounted for in the device model, the base-collector voltage at which impact-ionization-induced snap-back occurs can be accurately predicted