Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Time-domain model for power dissipation of CMOS buffers drivinglossy lines

The dynamic power consumption of a CMOS buffer driving lossless and lossy transmission lines is investigated. A time-domain model for power dissipation in both the line driver and the interconnect losses is also presented. The model fully agrees with HSPICE simulations and is particularly suitable for implementation in CAD tools for fast estimation of VLSI dissipation circuits     

Impact of charging efficiency variations on the effectiveness of variable-rate-based charging strategies for electric vehicles

The huge energy demand coming from the increasing diffusion of plug-in electric vehicles (PEVs) poses a significant challenge to electricity utilities and vehicle manufacturers in developing smart charging systems interacting in real time with distribution grids.These systems will have to implement smart charging strategies for PEV batteries on the basis of negotiation phases between the user and the electric utility regarding information about battery chemistries, tariffs, required energy and time available for completing the charging. Strategies which adapt the charging current to grid load conditions are very attractive. Indeed, they allow full exploitation of the grid capacity, with a consequent greater final state of charge and higher utility financial profits with respect to approaches based on a fixed charging rate.The paper demonstrates that the charging current should be chosen also taking into account the effect that different charging rates may have on the charging efficiency. To this aim, the performances of two smart variable-rate-based charging strategies, taken as examples, are compared by considering possible realistic relationships between the charging efficiency and the charging rate. The analysis gives useful guidelines for the development of smart charging strategies for PEVs as well as for next-generation battery charging and smart grid management systems.     

Time-domain macromodel for lossy VLSI interconnects

A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor     

TBM是怎样打洞的？

如果各位看过《十三罗汉》这部电影,那么肯定对片中的重要道具——隧道掘进机（Tunnel Boring Machine,缩写为TBM）印象深刻：巴舍·塔尔操作它使赌场产生共振,达到人造地震的效果,用来暂停班克酒店里的人工智能安全系统Greco。当然制造地震、挖金库、盗墓等只是TBM的副业,这种动辄几层楼高的“圆筒”的主要工作是挖掘隧道,比如电影中的那台就号称挖过英法海底隧道。     

Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.     

Video-assisted thoracoscopic surgery versus open thoracotomy for anterior thoracic spinal fusion. A comparative radiographic, biomechanical, and histologic analysis in a sheep model

STUDY DESIGN: In this in vivo investigation, a sheep model was used to compare the efficacy of a video-assisted thoracoscopic approach and a traditional thoracotomy in promoting a successful interbody spinal arthrodesis. OBJECTIVES: To compare the incidence of successful anterior spinal arthrodesis among three stabilization techniques-iliac crest, Bagby and Kuslich device, and Z-plate--performed using a video-assisted thoracoscopic approach and conventional open thoracotomy approaches. SUMMARY OF BACKGROUND DATA: A clinical outcome study on open versus endoscopic spinal fusion is not yet available. Moreover, no basic scientific investigations have been conducted to determine whether the success of an endoscopic arthrodesis is comparable to that of a conventional open procedure. METHODS: Fourteen Western Crossbred sheep underwent three identical destabilization procedures at T5-T6, T7-T8, and T9-T10, in which the anterior and middle osteoligamentous columns of the spine were resected, followed by three randomized reconstruction procedures using iliac autograft alone, and Z-plate stabilization with iliac autograft. In seven sheep, the entire destabilization-reconstruction procedure was performed using a video-assisted thoracoscopic surgical approach. In the remaining seven, the procedure was performed by conventional open thoracotomy. RESULTS: Histomorphometric and biomechanical evaluation demonstrated that the video-assisted thoracoscopic approach and open thoracotomy arthrodesis had comparable bone formation and biomechanical properties (P > 0.05). However, the Z-plate fusions, as a group, demonstrated increased flexion-extension stiffness properties and trabecular bone formation compared with the autograft and Bagby and Kuslich device fusions (P < 0.05). CONCLUSIONS: Thoracic interbody spinal fusions performed by thoracoscopy have demonstrated histologic, biomechanical, and radiographic equivalence to those performed by a thoracotomy approach. However, in the endoscopy group, intraoperative complications causing longer operative times, higher estimated blood loss, and increased animal morbidity indicated a substantial learning curve associated with the adoption of this surgical technique.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.