Oxidative catabolism of α-tocopherol in rat liver microsomes

The goal of this study was to clarify the mechanism responsible for the catabolism of α-tocopherol. The vitamin, bound to albumin, was incubated with rat liver microsomes and appeared to be broken down. Optimal production of the metabolite was obtained when 1 mg of microsomal protein was incubated with 36 μM of α-tocopherol in the presence of 1.5 mM of NADPH. Chromatographic and mass spectrometric analyses of the metabolite led to the conclusion that it consists of an ω-acid with an opened chroman ring, although we could not perform nuclear magnetic resonance analysis to confirm this. Our data show that α-tocopherol is ω-oxidized to a carboxylic acid and that this process can occur in rat liver microsomes in the presence of NADPH and O₂. The oxidation to the quinone structure appears to be a subsequent event that may be artifactual and/or catalyzed by a microsomal enzyme(s).     

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10^-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10^-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.     

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.     

Power and noise limitations of active circulators

In this paper, new simple formulas expressing the power and noise limitations for three three-way circulator architectures and three quasi-circulator architectures are derived. It is shown that the power-handling capability of the active three-way circulators is determined by the required transconductance of the transistors in the circuit, while the noise is determined by the drain noise current source. The suitability of the different active circulator architectures for transmit/receive applications is investigated, We conclude that the quasi-circulators based on passive isolation offer the highest performance     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

High-Q Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW     

Complementary high-voltage technology based on n-type CdSe:In andp-type Ge:Cu thin-film transistors

A breakthrough in the complementary thin-film transistor technology allows the production of voltage level shifters that raise a 5-V input span to an 80-V output span. The static and dynamic behavior of these level shifters is discussed. The present technology is applicable for the integration of driver circuits on the substrate of electroluminescent displays     

Load cell monitoring in Gas Centrifuge Enrichment Plants: Potentialities for improved safeguard verifications

This paper describes the principle of load cell monitoring in Gas Centrifuge Enrichment Plants (GCEPs) and how this technique can be implemented in order to improve nuclear safeguards in these kinds of installations.We present a few different possibilities of exploitation of the data that can be obtained by acquiring in continuous mode the weights of the cylinders in the feed and withdrawal (F/W) stations and how to derive conclusions concerning the operation of the plant (conformity or not with respect to “normal” operation).Furthermore the different diversion scenarios for GCEP are discussed and we show how mass monitoring techniques can contribute to detect each of them.Finally we resume the advantages and limitations of the technique and outline some important practical issues concerning the implementation of process monitoring in GCEP, in particular for what concerns the inspectorate/operator relationships.Load cell monitoring could play an important role in the safeguard implementation of future GCEPs.     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

Compact (<0.5mm2) K-band metamaterial bandpass filter in MCM-D technology

A bandpass filter based on complementary split ring resonators (CSRRs) and implemented in MCM-D technology is presented for the first time. It is a thin-film microstrip structure with CSRRs etched in the ground plane and interdigital capacitors in the signal strip. In addition, the structure includes grounded stubs. The combination of CSRRs and such stubs is useful to generate a transmission zero above the left-hand passband of the filter, and thus improve frequency selectivity. The filter, consisting of two CSRR cells, has a central frequency of f_o=19 GHz and a fractional bandwidth of FWB=18%. Inband return losses (RL=-15 dB) are satisfactory, while insertion losses (IL=-7.4 dB) are affected by the very small size of the resonant elements. Filter size is as small as 918times450 mum, i.e. 0.094 lambda_gtimes0.045lambda_g, where lambda_g is the guided wavelength at f_o. The implementation of these metamaterial-based structures in MCM-D technology opens new directions for the synthesis of ultra-small filters operating at millimetre wavelengths