Optimisation of direct digital frequency synthesisers based onCORDIC

Methods to simplify digital frequency synthesizers based on the co-ordinate rotation digital computer (CORDIC) algorithm are presented. Application of these methods leads to performance enhancement, compared with the topologies previously proposed in the literature. For a given output precision, hardware resources are reduced and spur-free dynamic range is increased     

Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling

There is not a single scaling technique that suits all kind of images. Final image quality (IQ) depends not only on the scale factor but also on the type of image (photo, CAD, Text...) the user is willing to print or display. Formally, any convolution-based scaling operation can be decomposed in three steps: an anti-aliasing filter, image reconstruction by continuous convolution and resampling to the final grid. Based on this formal framework, we propose a flexible hardware-friendly architecture to perform two-dimensional upscaling and downscaling at low hardware cost. In particular, we propose a discrete convolution engine operating a memory that stores a programmable 2-D-separable interpolation kernel. We also state a technique for optimizing the memory size given the kernel and the scale factor. Finally, we describe a novel flexible filter that overcomes aliasing artifacts regardless of image frequency content. The flexibility provided by the combination of the aforementioned elements allows the user to adjust the interpolation kernel and parameters to each specific type of image for IQ improvement.     

Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing

Two-dimensional convolutions are local by nature; hence every pixel in the output image is computed using surrounding information, i.e., a moving window of pixels. Although the operation is simple, the hardware is conditioned by the fact that due to bandwidth efficiency full raster rows must be read from the external memory, and that a row-major image scan should be performed to support shift-variant convolutions. When extending the architectures developed in prior-art to support shift-variant convolutions, we realize that they require large amounts of on-chip memory. While this fact may not have a large cost increase in ASIC implementations, it makes field-programmable gate arrays (FPGA) implementations expensive or not feasible. In this paper, we propose several novel FPGA-efficient architectures for generating a moving window over a row-wise print path. Because the proposed concepts have different throughput and resource utilization, we provide a criteria to choose the optimum one for any design point.