Micro breakdown in small-area ultrathin gate oxides

The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.     

Single-ion dosemeter based on floating gate memories

Floating Gate (FG) nonvolatile memories are based on a tiny polysilicon layer (the FG) which can be permanently charged with electrons or holes, thus changing the threshold voltage of a MOSFET. Every time a FG is hit by a high energy ion, it experiences a charge loss, depending on the ion linear energy transfer (LET) and on the transistor geometrical and electrical characteristics. This paper discusses the opportunities to use this devices as single an ion dosemeter with sub-micrometer spatial resolution and capable of distinguish the impinging ion LET.     

Sensitivity and dynamic range of FGMOS dosemeters

UVPROM memory devices employing FGMOS transistors as memory cells make excellent dosemeters for applications involving ionising radiation. With proper preparation and programming, these devices can be used in remote-sensing applications in high-radiation environments with no power required during exposure.     

A review of ionizing radiation effects in floating gate memories

The effects of ionizing radiation on microelectronics are traditionally a concern for devices intended for the space use, but they are becoming important even at ground level. Ionizing radiation effects can be broadly divided in two classes: total ionizing dose (progressive buildup of defects) and single event effects (macroscopic result of a single microscopic event). In both cases, ionizing radiation can lead to severe degradation of device performance, possibly resulting in device failure. This work is a review of literature results concerning both classes of ionizing radiation-related phenomena on floating gate memories. Regardless of its nature, ionizing radiation impacts two aspects of the performance and reliability of floating gate memories: the functionality and the adherence to specifications of the control circuitry, and the degradation of stored information in the array itself.     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

Different nature of process-induced and stress-induced defects in thin SiO/sub 2/ layers

High-temperature anneal in hydrogen ambient is performed at the end of a CMOS manufacturing process to recover the process-induced defects. The authors focus on the recovery and wearout of thin gate oxides (3.3 nm) during repetitive stress-anneal-stress cycles. Thermal annealing at 450 /spl deg/C leads to detrapping phenomena and to the complete recovering of electrically induced defects. On the other hand, the same thermal annealing is not capable of fully recovering the process-induced damage. The kinetic of defect recovering (and not the number of defects annealed out) strongly depends on the amount of latent damage.     

Identification of Crims Model Parameters for Warpage Prediction in Injection Moulding Simulation

Polymer injection moulding is a process widely used to produce components in a lot of different applications. One of the most critical aspects related to this process is to control the warpage of the parts after the extraction from the mould. Numerical simulations can predict a part warpage by using specific warpage models. Among numerical codes, Autodesk Moldflow Insight® uses a Corrected In Mold Residual Stress (CRIMS) model, that calculate the residual stresses develop during the moulding process. Warpage is then predicted calculating the deformations of the component induced by the considered stresses. Using experimental and numerical techniques, a new identification procedure was introduced to evaluate the six parameters of the CRIMS model included in the Moldflow® material properties database. The study was conducted on a box for an automotive application made of polypropylene. On the base of a complete rheological, thermal and physical characterization of the employed material, a numerical simulation of the process was implemented, integrating it with an optimization procedure to identify the values of the CRIMS parameters that force numerical results to fit measured deformations. As this procedure was very time consuming, requiring to run several computationally intensive simulations, artificial neural networks were employed to approximate numerical results with lower computational time. Results were verified with independent samples, showing good correspondence between experimental results and numerical calculated deformations.     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

Low-field latent plasma damage depassivation in thin-oxide MOS

A novel plasma-process induced damage depassivation method is proposed. Using a staircase-like stress voltage and varying the stress time, we were able to depassivate the latent damage at very low-field on both nMOS and pMOS devices. The dynamic of the interface traps generation is studied; pMOS devices show a peculiar behavior, which can be explained understanding the mechanisms involved in damage depassivation. The energy of carriers is identified as the damaging factor.     

Radiation-induced depassivation of latent plasma damage

Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/SiO₂ interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices.