Optical and mechanical performance of a novel magnetically actuated MEMS-based optical switch

A novel magnetically actuated 8/spl times/8-port MEMS-based fiber-optic switch is described. Fiber-to-fiber insertion loss measurements of six 8/spl times/8 switch units show average and worst-case insertion loss of 1.3 dB and 2 dB, respectively. Low insertion loss is achieved through a unique MEMS design that uses anisotropically etched single-crystal silicon sidewalls to provide a global mechanical alignment stop for an array of MEMS mirrors. This alignment surface produces a uniform and repeatable mirror angle across the mirror array. Mirror misalignment is attributed to the surface roughness of the silicon sidewalls. Repeated interferometric measurements of the mirrors of 24 8/spl times/8 switch units show repeatability of the mirror angle of 3/spl times/10/sup -3/ degrees, while the uniformity of the mirror angle across the MEMS array is 2/spl times/10/sup -2/ degrees, in agreement with the angular error predicted from measurements of sidewall surface roughness. In turn, the average repeatability and uniformity of the insertion loss are 0.01 dB and 1 dB, respectively, in agreement with predictions based on the interferometric measurements. Finally, the unique dynamics of the magnetic actuation and electrostatic addressing scheme are described. Measurements show that fast switching can be achieved by driving the mirrors with a magnetic pulse that is faster than the mechanical resonant frequency of the mirror, relying on an electrostatic clamping force to capture the mirror as it overshoots the magnetic field angle. This actuation scheme is shown to result in switching times of 8.5 ms to 13.5 ms, but requires accurate control of the kinetic energy of the mirror.     

Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30 V range. These circuits combine high-performance CMOS with a high-voltage MOS transistor. A possible choice for the high-voltage device is an n-channel lateral DMOS (NLDMOS) transistor. An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet safe operating area (SOA) and hot carrier (HC) reliability requirements. This paper focuses on understanding anomalous SOA and HC results obtained from an NLDMOS transistor whose drain drift implant dose was varied     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

Evaluation of performance–reliability trade-offs in a Si–Ge BiCMOS process using fast wafer level techniques

Fast wafer-level reliability (fWLR) techniques are successfully implemented in order to investigate several gate oxide reliability–performance tradeoffs that affect the architecture of a high speed BiCMOS process. Fast feedback of device and reliability parameters is required during process development in order to avoid failures during process qualification. This study highlights some performance–reliability tradeoffs that had to be overcome during the development of a modern BiCMOS process.     

A new physics-based model for time-dependent Dielectric breakdown

A physics-based model for time dependent dielectric breakdown has been developed, and is presented along with test data obtained by NIST on oxides provided by National Semiconductor. Testing included fields from 5.4 MV/cm to 12.7 MV/cm, and temperatures ranging from 60 °C to 400 °C. The physics, mathematical model, and test data, all confirm a linear, rather than an inverse field dependence. The primary influence on oxide breakdown was determined to be due to the dipole interaction energy of the field with the orientation of the molecular dipoles in the dielectric. The resultant failure mechanism is shown to be the formation and coalescence of vacancy defects, similar to that proposed by Dumin et al.     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

Impact of NBTI and HCI on PMOSFET threshold voltage drift

Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, V_t-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.     

Influence of mobility model on extraction of stress dependent source–drain series resistance

The extraction of the parasitic source–drain series resistance after stress is a significant challenge, which has not been reported for channel lengths below 0.5 μm. Methods proposed until now yield a reducing series resistance behaviour for such channel lengths, contrary to expectation. We demonstrate that the underlying cause of this phenomenon is due to modification of mobility behaviour under stress. A new methodology for monitoring the time dependent progression of series resistance and mobility degradation for stress conditions varying from hot carriers to Negative Bias Temperature is proposed. A new threshold voltage model separating the effects of damaged and undamaged portions of a stressed device is also demonstrated.     

Influence of test techniques on soft breakdown detection in ultra-thin oxides

This paper presents soft breakdown (SBD) measurement results on ultra-thin oxides and shows that constant current stress and constant voltage stress SBD measurements do not yield equivalent time-to-failure results. Correlation issues that exist between the two techniques include the percentage of detected SBD events, the post-SBD noise and current–voltage (I–V) behavior. To understand the differences between these two measurement techniques the effect of stress source power on the SBD event is examined. It is found that limiting the available source power during stress significantly impacts the detection and post I–V behavior of the SBD event.