Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

Re-oxidation characteristics of oxynitrides on 3C- and 4H-SiC

N₂O annealing of oxides in both Si and SiC is known to result in a similar accumulation of nitrogen at the semiconductor-oxide interface, but the reoxidation of oxynitrides is different in these materials. With Si, the nitrogen at the interfl￡e is unaffected upon re-oxidation even under high oxidant flow conditions. With SiC, as shown in this paper, complete depletion of the nitrogen from the interface is observed with the re-oxidation of SiC oxynitrides for both 3C and 4H polytypes. The depletion of the nitrogen from the interface is strongly dependent on the re-oxidation temperature. Results are described and a possible mechanism proposed.     

High-voltage lateral RESURF MOSFETs on 4H-SiC

High-voltage lateral RESURF MOSFETs have been fabricated on 4H-SiC with both nitrogen and phosphorus as source/drain and RESURF region implants. Blocking voltages as high as 1200 V and specific on-resistances of 4 Ω cm² have been obtained, with the high on-resistance attributed to poor inversion layer mobility. Phosphorus is most appropriate for the source/drain implants due to low sheet resistance and contact resistance with low temperature anneals. However, poor activation of low dose phosphorus implants at 1200°C makes nitrogen the preferred choice for the RESURF region     

Hysteresis in transfer characteristics in 4H-SiCdepletion/accumulation-mode MOSFETs

Hysteresis in room-temperature transfer characteristics between forward (pinch-off voltage, V_P=-15 V) and reverse gate voltage sweeps (V_P=7 V) in n-channel depletion/accumulation-mode 4H-SiC MOSFETs is reported. Transfer characteristics exhibit a parallel shift toward negative voltages depending,on the starting gate voltage and direction of the sweep. The hysteresis and shift in transfer characteristics are related to changes in effective fixed-oxide charge resulting from changes in interface trap occupancy. Interface trap occupancy changes depending on the magnitude of the starting gate voltage and the direction of gate-voltage sweep. At high temperatures, the hysteresis between forward and reverse gate voltage sweep decreases     

The effect of learning by imitation on a multi-robot system based on the coupling of low-level imitation strategy and online learning for cognitive map building

It is assumed that future robots must coexist with human beings and behave as their companions. Consequently, the complexities of their tasks would increase. To cope with these complexities, scientists are inclined to adopt the anatomical functions of the brain for the mapping and the navigation in the field of robotics. While admitting the continuous works in improving the brain models and the cognitive mapping for robots’ navigation, we show, in this paper, that learning by imitation leads to a positive effect not only in human behavior but also in the behavior of a multi-robot system. We present the interest of low-level imitation strategy at individual and social levels in the case of robots. Particularly, we show that adding a simple imitation capability to the brain model for building a cognitive map improves the ability of individual cognitive map building and boosts sharing information in an unknown environment. Taking into account the notion of imitative behavior, we also show that the individual discoveries (i.e. goals) could have an effect at the social level and therefore inducing the learning of new behaviors at the individual level. To analyze and validate our hypothesis, a series of experiments has been performed with and without a low-level imitation strategy in the multi-robot system.     

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.     

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs

We report the characterization of diode and bipolar triggered SCRs with VFTLP measurements and product ESD testing. A dual base Darlington bipolar triggered SCR (DbtSCR) in a triple well structure is demonstrated to provide 4 kV HBM, 300 V MM, and 1000 V CDM protection for 90 nm ASIC I/Os. A very fast turn-on time of 460 ps was measured for the DbtSCR, compared to 8 ns for a diode triggered SCR.     

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by 50% with respect to a design where ED is not located under the contacts.