Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO₂) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.     

Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET

Silicon - This work presents the analog and RF performance evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have been compared...     

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping (N_A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency (f_t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain (Gma), maximum transducer power gain (G_MT), maximum unilateral power gain (MUG), maximum frequency of oscillation (f_MAX) and stern stability factor (K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.     

Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance

Silicon - In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at...     

Effect of structured parameters on the hot-carrier immunity of transparent gate recessed channel (TGRC) MOSFET

In this work, the impact of parameter variation on hot-carrier effect immunity in transparent gate recessed channel (TGRC)—MOSFET based on the hydrodynamic energy transport model have been studied. The parameters of TGRC-MOSFET investigated include the oxide thickness, negative junction depth, and substrate doping. TCAD analysis shows the performance of TGRC-MOSFET in terms of transfer characteristics, transconductance, electric field, electron velocity, electron mobility and electron temperature. The simulation results indicate the improved hot-carrier immunity for TGRC-MOSFET in 30 nm device.

     

Analysis of a Novel Nanoscale Vacuum Channel TF-FinFET

Silicon - Concerned work is solely dedicated to the optimized characteristics of Nanoscale vacuum channel TF (Truncated fin)-FinFET at gate length of 7 nm. NVCTF-FinFET has its own...     

Mapping of debris-covered glaciers in the Garhwal Himalayas using ASTER DEMs and thermal data

Mapping of debris-covered glaciers using remote-sensing techniques is recognized as one of the greatest challenges for generating glacier inventories and automated glacier change analysis. The use of visible (VIS) and near-infrared (NIR) bands does not provide sufficient continual information to detect debris-covered ice with remote-sensing data. This article presents a semi-automated mapping method for the debris-covered glaciers of the Garhwal Himalayas based on an Advanced Spaceborne Thermal Emission and Reflection Radiometer (ASTER) digital elevation model (DEM) and thermal data. Morphometric parameters such as slope, plan curvature and profile curvature were computed by means of the ASTER DEM and organized in similar surface groups using cluster analysis. A thermal mask was generated from a single band of an ASTER thermal image, while the clean-ice glaciers were identified using a band ratio based on ASTER bands 3 and 4. Vector maps were drawn up from the output of the cluster analysis, the thermal mask and the band ratio mask for the preparation of the final outlines of the debris-covered glaciers using geographic information system (GIS) overlay operations. The semi-automated mapped debris-covered glacier outline of Gangotri Glacier derived from 2006 ASTER data varied by about 5% from the manually outlined debris-covered glacier area of the Cartosat-1 high-resolution image from the same year. By contrast, outlines derived from the method developed using the 2001 ASTER DEM and Landsat thermal data varied by only 0.5% from manually digitized outlines based on Indian Remote Sensing Satellite (IRS)-1C panchromatic (PAN) data. We found that post-depositional sedimentation by debris flow/mass movement was a great hindrance in the fully automated mapping of debris-covered glaciers in the polygenetic environment of the Himalayas. In addition, the resolution of ASTER stereo data and thermal band data limits the automated mapping of small debris-covered glaciers with adjacent end moraine. However, the results obtained for Gangotri Glacier confirm the strong potential of the approach presented.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.