Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si_0.57Ge_0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm.     

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.     

Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes

Strained silicon-germanium (Si_0.6Ge_0.4) gated diodes have been fabricated and analyzed. The devices exhibit significantly enhanced gate-controlled tunneling current over that of coprocessed silicon control devices. The current characteristics are insensitive to measurement temperature in the 80 K to 300 K range. Independently extracted valence band offset at the strained Si_0.6Ge_0.4/Si interface is 0.4 eV, yielding a Si_0.6Ge_0.4 bandgap of 0.7 eV, which is much reduced compared to that of Si. The results are consistent with device operation based on quantum-mechanical band-to-band (BTB) tunneling rather than on thermal generation. Moreover, simulation of the strained Si_0.6Ge_0.4 device using a quantum-mechanical BTB tunneling model is in good agreement with the measurements.     

Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si/sub 0.4/Ge/sub 0.6/ on relaxed Si/sub 0.7/Ge/sub 0.3/ are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2.3X at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1.8X) for 10- and 5-nm-thick Si cap samples, which reduces to 1.6X for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec, compared to that for the Si control.