On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs     

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.     

Theoretical considerations for SRAM total-dose hardening

The theoretical hardness against total dose of the six-transistor SRAM cell is investigated in detail, an explicit analytical expression of the maximum tolerable threshold voltage shift is derived for two cross-coupled inverters. A numerical method is used to explore the hardness of the read and write operations. Both N- and P-channel access transistors designs are considered and their respective advantages are compared. The study points out that the radiation hardness mainly relies on the technology. Results obtained with the very robust Gate-All-Around process are finally presented     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

Surface activation using oxygen and nitrogen radical for Ge-Si Avalanche photodiode integration

In this work, an alternative method for producing the single crystalline Ge-Si Avalanche photodiodes (APD) with low thermal budget was investigated. Structural and electrical investigations show that low temperature Ge to Si wafer bonding can be used to achieve successful APD integration. Based on the surface chemistry of the Ge layer, the buried interfaces were investigated using high resolution transmission electron microscopy as a function of surface activation after low temperature annealing at 200 and 300 °C. The hetero-interface was characterized by measuring forward and reverse currents.     

Total gamma dose characteristics of CMOS devices in SOI structuresbased on oxidized porous silicon

The electrical characteristics of complementary metal-oxide-semiconductor (CMOS) transistors and ring oscillators fabricated in porous silicon silicon-on-insulator (SOI) structures are presented before and after gamma irradiation. P-channel SOI/MOS transistors exhibit a front-gate threshold voltage shift of -0.2 and -0.55 V after exposure to doses of 1 and 10 Mrad(Si), respectively, under floating bias conditions, which are different from worst case conditions. For n-channel transistors the corresponding values are -0.1 and -0.2 V. The additional bottom and sidewall B⁺ ion implants with a dose of 2×10¹³ cm^-2 are found to be effective to prevent leakage current along the n-channel transistor bottom and sidewalls. SOI/CMOS ring oscillators present a 40% higher speed in comparison with the same bulk CMOS devices and continued stable operation under a supply voltage of 3-5.5 V, for gamma irradiation up to 10 Mrad(Si), and an operating temperature ranging from 77 to 400 K     

Multiple-gate SOI MOSFETs: device design guidelines

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.     

Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.     

Bulk traps in ultrathin SIMOX MOSFET's by current DLTS

Bulk traps in very thin ( ~100-nm) SIMOX films have been studied by applying current deep-level transient spectroscopy (DLTS) to fully depleted, enhancement MOS transistors, fabricated in these films. The effect of states at both the front and back SiO₂-Si interfaces is eliminated by suitable biasing. Using this technique, a bulk trap with energy level 0.44 eV above the valence-band edge, capture cross section ~10^-17 cm², and concentration ~10 ¹⁵ cm^-3, which is believed to be due to iron contamination, has been identified     

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect