Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

Thermionic Emission as a Tool to Study Transport in Undoped nFinFETs

Thermally activated subthreshold transport has been investigated in undoped triple-gate MOSFETs. The evolution of the barrier height and of the active cross-sectional area of the channel as a function of gate voltage has been determined. The results of our experiments and of the tight-binding simulations we have developed are both in good agreement with previous analytical calculations, confirming the validity of the thermionic approach to investigate transport in FETs. This method provides an important tool for the improvement of device characteristics.      

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs

A comparative investigation of high-energy neutrons effect on strained and non-strained devices with different geometries is presented. Both single-gate planar and multiple-gate (MuG) silicon-on-insulator (SOI) devices are considered. Device response to the neutron irradiation is assessed through the variations of threshold voltage and transconductance maximum. The difference between strained and non-strained device response to the high-energy neutrons exposure is clearly evidenced. The reasons for such a difference are discussed. Analysis of the experimental results allows for suggesting that strain relaxation is one of the probable causes.     

Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects

In this letter, we modify the split capacitance-voltage technique to exclude the influence of floating-body effects on the extracted mobility values and extend its applicability by using the integral of transconductance measured at high frequencies instead of dc drain current values. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating-body effect, which is an inevitable feature of advanced silicon-on-insulator MOSFETs, but also to improve the general accuracy of mobility extraction in moderate-to-strong inversion regime. We demonstrate the advantages of our modified technique over the conventional one by applying it to partially depleted silicon-on-insulator devices from a FinFET process.     

On the reverse short channel effect in deep submicronheterojunction MOSFET's and its impact on the current-voltage behavior

In this paper, we report on the reverse short channel effect (RSCE) in vertical heterojunction MOSFET's, which use a source/channel heterojunction for reduction of the short channel effect (SCE) in deep submicron devices. The study shows that a typical RSCE will occur when the heterobarrier dominates the channel potential and when the barrier is strong enough to shift the potential maximum (pMOS) or minimum (nMOS) toward the source/channel interface. The particular channel potential for these devices will give rise to a current-voltage (I-V) behavior which deviates from the classical linear or saturation regime for homojunction devices. A distinctive “transition zone” needs to be taken into account     

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.     

Advanced CMOS device technologies for 45 nm node and below

We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG) candidates for scaled CMOS technologies are fully silicided (FUSI) gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-V_T) are reported (17 ps at V_DD=1.1 V and 20 pA/μm I_off), meeting the ITRS 45 nm node requirement for low-power (LP) CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress) or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.     

Limitations of shift-and-ratio based Leff extractiontechniques for MOS transistors with halo or pocket implants

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel transistor to be equal. Scaling down the MOS transistor urges the need of including halo (or pocket) implants in the fabrication process. Due to this implant, however, the short channel MOSFET features a degraded effective mobility compared to the long channel reference device. This affects the channel-length extraction and results in unrealistic high values for the extracted effective channel-length for deep submicron transistors with high-dose halo (or pocket) implants