1.1 GHz oscillator using bondwire inductance

Using the parasitic inductance usually associated with a bondwire in an IC package, a bipolar GHz LC-tuned oscillator is designed. Bondwires have very low series resistance and are thus suitable for high-Q applications. Measured results indicate very low phase noise and low power consumption     

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiralinductors

A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range     

Green Reconfigurable Radio Systems

The wireless standards scene and its evolution strengthens the need for functional flexibility in future radios. Multimode terminals supporting an increasingly large variety of standards (cellular, WLANs, WMANs, WPANs) are subject to a cost increase that is addressed by more flexible radio interfaces. Energy efficiency, however, is the main obstacle to successfully deploying such reconfigurable radios. To address this, it is essential to design energy-scalable SDRs, both for the radio front-end and the digital baseband platform. Complementing this, an essential ingredient is an intelligent controller that optimally exploits this scalability and the run-time dynamics to translate potential energy scalability to actual low-power operation. To realize this goal, an energy-aware cross-layer radio management framework is introduced. It was instantiated in different case studies, showing the applicability of this approach in realistic setups. Results have shown that substantial gains can be achieved through effective cross-layer optimization and problem partitioning. Next, it was shown that SDRs will play a crucial role in enabling CRs, which will enable saving on both the scarce radio spectrum and battery lifetime. A key building block for the design of such CRs, i.e., the appropriate control intelligence to make the SDR platform cognitive, can be derived by incrementally building on the proposed framework. As a result, green (or environment friendly) reconfigurable radio systems will emerge, which offer a wide variety and ubiquitous availability of wireless services, while overcoming energy and spectrum scarcity     

Direct digital-RF amplitude modulator in CMOS 90nm

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segment-addressed resulting in a very compact 0.007 mm² chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.     

A CMOS rectifier-integrator for amplitude detection in hard diskservo loops

In this paper a CMOS alternative amplitude detection system is presented. It is designed as an alternative for the, bipolar, amplitude detection in hard disk servo systems. The amplitude is detected by converting the input voltage to a current, rectifying the current, and integrating it on a capacitor. For this a new OTA topology and a rectifier cell are designed. This circuitry is expanded with a very linear current mirror and an automatic offset compensation system to cope with technology spread. The measured accuracy of the amplitude detector is 0.2% (9 b). This makes the circuit suitable for implementation in state-of-the art hard disk systems with very high track densities and very short access times. Because the circuit is realized in standard CMOS it is a further step toward CMOS only hard disk electronics. Because the circuit operates from a single 3 V power supply and has limited power consumption it can be used in battery powered systems     

Spatially oversampled TDC with digital resolution enhancement

A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time interval with low complexity TDC of varying low resolutions. The coarse outputs of each converter are digitally post-processed to obtain an output whose precision is much better than that of the individual converters. Three post-processing algorithms are proposed and their limitations in presence of converter non-idealities are analyzed. A prototype system with 8 channels is implemented in 90 nm CMOS. 40MS/s output of each channel is algorithmically combined to obtain over 2.2–3X measured improvement in the resolution in 4/6/8 channel modes, validating the system principle. The chip occupies 0.3 mm² and draws up to a maximum of 4 mA from a 1.2 V supply.     

Fully Integrated Low Phase-Noise VCOs: From Special Processing to Standard CMOS

An overview is given on the several options for and problems associated with creating high-quality integrated inductors for VCOs. Special processing techniques are reported that can enhance the performance of a normal planar inductor coil. Bonding Wire inductors are presented as an alternative, that allows state-of-the-art phase noise performance at no extra cost. Finally, it is shown that by thorough analysis of standard planar inductors with finite-element simulations, performances can be achieved that are even better than structures requiring extra processing cost. This is done despite a low-ohmic substrate with only two metal layers.     

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.     

Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

As the tuning range of integrated LC-VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor size optimally for the complete frequency range. The presented VCO design solves this by adjusting the size of the negative resistance transistors with a switched active core, with the additional benefit that this reduces parasitics and hence allows to achieve better phase noise and an even higher tuning range. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13-mum CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 7.7 to 2.1 mA from a 1.2 V supply. The measured phase noise is -118 dBc/Hz at 1 MHz from a 4-GHz carrier.     

A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset