A 10-bit 250-MS/s binary-weighted current-steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.     

Application of High-Speed, High-Accuracy Dacs for Generation of Multiple Channels

Most modern communication systems use frequency division multiplexing to serve more than one customer. The combination of FDM signals in the digital domain has several advantages over analog approaches. We show what DAC specifications are needed to build such systems and explain important limiting factors. Special attention is given to the multi-channel generation issues. This reveals that in some cases the DAC specifications are less stringent than what is generally expected. Jurgen Deveugele was born in 1976 in Kortrijk, Belgium. He received his masters degree in electronic engineering in 1999 at the Katholieke Universiteit Leuven, Belgium. He is currently working to wards a Ph.D. at Micas, Katholieke Universiteit Leuven, Belgium. His main research interests are in low-power and high-speed current-steering digital-to-analog converters. Michiel S.J. Steyaert was born in Aalst, Belgium, in 1959. He received the masters degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (K.U. Leuven), Heverlee, Belgium in 1983 and 1987, respectively. From 1983 to 1986 he obtained an IWNOL fellowship (Belgian National Fundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT at K.U. Leuven. In 1987 he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988 he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989 he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992 as a Senior Research Associate and in 1996 as a Research Director at the Laboratory ESAT, K.U. Leuven. Between 1989 and 1996 he was also a part-time Associate Professor. He is now a Full Professor at the K.U. Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Prof. Steyaert received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications. Prof.Steyaert received the 1995 and 1997 IEEE-ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and is currently an IEEE-Fellow.     

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC

This brief analyzes the systematic errors that limit the intrinsic accuracy of a digital-to-analog converter (DAC). A new switching scheme is proposed that exhibits special properties: it cancels the linear and quadratic gradient errors at the MSB level. We explain why this scheme has those properties and how to construct it. This scheme excels at reducing edge-effects occurring at the side of the array. No extracted information from the error profile is required. This increases the robustness of the scheme and reduces the need for reprocessing. The effectiveness of this scheme is demonstrated by applying it to the measured error profile of a 14-b current-steering converter without dummies. This shows that 14-b current-steering converters can be constructed without any dummy rows or columns at all.     

Parallel-path digital-to-analog converters for Nyquist signal generation

Nyquist-rate digital-to-analog converters (DACs) can generate frequencies up to half the sampling frequency. It is, however, impractical to generate such high frequencies. Due to its nature, the converter will not only generate the desired signal itself but also, often undesired, image frequencies. For frequencies near the Nyquist frequency, an image with almost exactly the same amplitude appears very close to the signal. An extremely steep filter is required. Therefore, real-life systems do provide oversampling to locate the Nyquist image further away from the wanted signal. In practice, the signal frequency has to be reduced if the maximum sampling rate is reached. We propose a technique that conversely removes this Nyquist image so that only further away Nyquist images with lower amplitudes have to be filtered off. The proposed technique is applied to the design of a dual 6-bit binary current-steering DAC running at 250 MS/s.