Activation energy determination from low-temperature CV dispersion[semiconductor devices]

The response of semiconductor devices at low temperatures to changes in the voltage across the depletion region is limited by the dielectric relaxation time of the majority carriers in the bulk region. This results in a dispersion of the C-V curves at low temperatures. In this paper, we report a study of the dispersion seen in the accumulation and depletion regions of the C-V curve in n- and p-channel MOS transistors as well as in reverse biased one-sided abrupt junctions. From the admittance measured as a function of temperature and frequency, the dopant energy level is determined. The values of the activation energy measured using the diodes agree well with the corresponding values obtained using MOS devices     

Low-temperature CV dispersion in MOS devices

A study is reported of the dispersion seen in the accumulation and depletion regions, of the C-V curve in n-channel MOS devices in the temperature range 30-45 K. It is concluded that the dispersion observed in these experiments is caused by time-constant effects, due to the substrate resistance and not caused by dopant atom emission time constant effects. From the measured admittance as a function of temperature and frequency, the acceptor energy level is determined to within ±0.4 meV     

Quasi-static behavior of MOS devices in the freeze-out regime

The quasi-static CV curves (low-frequency C-V curves) measured in the freeze-out regime of MOS transistors result in peaks near the accumulation or inversion regions depending on the direction of the voltage sweep. In this paper, we report a study of these peaks in n- and p-channel CMOS transistors within and outside compensating wells. The peaks in the quasi-static CV curves are attributed to the capture of minority carriers near inversion by the interface states and the capture of majority carriers by the interface states near accumulation     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

Effect of plasma poly etch on effective channel length and hotcarrier reliability in submicron transistors

The effective channel length (L_eff)) variation resulting from exposure to the plasma during the poly-etch step was investigated. The plasma induced charging effect was also studied using gate polysilicon antenna structures. It was found that, due to the poly etching, the L_eff variation has a larger impact on the fully processed transistor transconductance characteristics than the charging effect in the gate oxide region. It is believed that the damage in the LDD region, which gives rise to the L_eff variation, imposes a serious hot carrier reliability problem     

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

In this letter, we present a novel junction integration scheme that enables vertical transistors to have high performance, low leakage, and easy scalability. Controlled solid-phase diffusion is used to form the vertically self-aligned buried strap junction of the vertical transistor. The electric field at the capacitor node junction is carefully optimized by creating a graded junction profile, resulted from a combination of out-diffusion from Arsenic-doped poly-silicon and Phosphorus-doped oxide. The Phosphorus-doped oxide serves as the dopant source for the vertical lightly doped drain, as well as the spacer for the high dose junctions. Integration of the self-aligned junctions into a vertical transistor dynamic random access memory (DRAM) process flow is presented. Significant improvement in the retention characteristics of a 256-Mb DRAM product confirms the applicability of this newly developed junction integration scheme for future DRAM generations.     

Reactor safety research - visible demonstrations and credible computations

The Electric Power Research Institute has been conducting nuclear safety research for a number of years with the primary goal of assuring the safety and reliability of the nuclear plants. The visibility is emphasized by sponsoring or participating in large scale test demonstrations to credibly support the complex computations that are the basis for quantification of safety margins.Recognizing the success of the airline industry in receiving favorable public perception, the authors compare the design and operation practices of the airline industry with those of the nuclear industry practices to identify the elements contributing to public concerns and unfavorable perceptions.In this paper, authors emphasize the importance of proper communications of research results to the public in a manner that non-specialists understand. Further, EPRI supported research and results in the areas of source term, seismic and structural engineering research, analysis using probalistic risk assessment (PRA), quantification of safety margins, digital technology development and implementation, and plant transient and performance evaluations are discussed in the paper.     

Signal validation techniques and power plant applications

Computerized signal validation is a software technique for integrating information from redundant and from functionally diverse sensors to provide highly reliable information to operating crews and to auto matic controllers. High reliability results from greater and more comprehensive use of existing sensor redundancy, and from inherent fault detection and isolation (FDI) of faulty sensors.

Operating crews at power plants have always performed some measure of manual signal validation. With the current thrust to introduce digital computers to support plant monitoring and operator aid functions# signal validation has become generally recognized as a key element in the interface between plant sensors and algorithms using sensor data. For any computerized system to be robust and to yield a false alarm rate that is credibly low, high information reliability must be assured at the front end.

Progress of research in computerized signal validation techniques has benefited the U.S. utilities by improving the reliability of safety parameter display systems (SPDS) implemented in the nuclear power plants. Conventional signal validation techniques have been combined with more robust parity space and analytic redundancy methods to provide reliable and real-time SPDS monitoring information to PWR and BWR operators. The technical details of the methods, application to PWR and BWR SPDS, and the extension of the techniques to plant control functions are reviewed in this paper.