A 20-GHz InP-HBT voltage-controlled oscillator with wide frequencytuning range

This paper presents the design and implementation of a 20-GHz-band differential voltage-controlled oscillator (VCO) using InP heterojunction-bipolar-transistor process technology. Aimed at 20- or 40-Gb/s fiber-optic applications, the design is based on a single-stage feedback amplifier with no intentional L or C. The salient features of the proposed VCO are wide frequency tuning range compared to LC oscillators, and low power consumption and transistor count compared to ring-oscillator counterparts. The implemented VCO has an adjustable frequency range from 13.75 to 21.5 GHz and provides two complementary outputs. Total power consumption at 18.6 GHz is 130 mW, while the phase noise is -90.0 dBc/Hz measured at 1-MHz offset frequency     

Differential CMOS circuits for 622-MHz/933-MHz clock and datarecovery applications

This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-μm CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s