Determination of combinational logic circuit reliability through generation of fault diagnosis tests

This paper investigates the relationships between a given set of excitation vectors and the test sets for faults occuring in combinational circuits, in order to obtain new conditions for determining the redundant cubes of terminal states. The analysis presented is concluded with two new algorithms for the evaluation of combinational logic circuit reliability.     

Recursive enumeration of state graphs for the reliability evaluation of logic circuits

A method is presented for the recursive enumeration of State Graphs in a given Circuit Equivalent Graph [1] for logic circuit reliability evaluation purposes. This enumeration is quite complicated and requires the systematic searching through the Circuit Equivalent Graph. The enumeration is accomplished by symbolic notation, which is a powerful tool for denoting State Graphs. The state-graph expression in symbolic form (SG-expression) is a string of literals and arc symbols and maps uniquely a given State Graph. Using a Last-In-First-Out manipulation approach and assuming appropriate rules for the ordering of State Graphs, an enumeration algorithm is developed which satisfies two important objectives; namely, the total enumeration of SG-expressions from a Circuit Equivalent Graph and the recursive searching of SG-expressions which correspond to a given cube of terminal states.     

A cubical logic circuit modelling for reliability studies

A deeper insight into the problem of reliability analysis for combinational logic circuits is presented. Reliability is defined as the probability that the logic circuit correctly processes a given set of inputs. While the straightforward approach to this evaluation requires a formidable amount of computations, the presented approach is fast, easy to implement, memory efficient and applicable to circuits of any size and complexity. This is due to a new concept for logic circuit modelling, which allows the covering of all possible faults in a circuit by a relatively small number of sets of logically equivalent faults.For modelling purposes the excitations of inputs and the states of terminals in logic gates are presented in the form of a state vector. The logically equivalent state vectors are merged to form highest-order cubes which are mapped onto a gate equivalent graph (GEG). According to the connections among gates in the logic circuit this graphical model is extended to the circuit equivalent graph (CEG), which comprises the highest-order cubes for a circuit in the form of appropriate subgraphs, the so called state graphs (SGs).     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed