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排序方式: 共有48条查询结果,搜索用时 15 毫秒
1.
An EMI estimate for shielding-enclosure evaluation   总被引:7,自引:0,他引:7  
A relatively simple, closed-form expression has been developed to estimate the EMI from shielding enclosures due to coupling from interior sources through slots and apertures at the enclosure cavity modes. A power-balance method, Bethe's (1944) small-hole theory, and empirically developed formulas for the relation between radiation, and slot length and number of slots, were employed to estimate an upper bound on the radiated EMI from shielding enclosures. Comparisons between measurements and estimated field strengths suitably agree within engineering accuracy  相似文献   
2.
A first-order behavioral IGBT/gate drive model is proposed together with a procedure for deriving all model parameters. Despite the simplicity of the proposed model, comparison of model predictions with hardware measurements demonstrate the model to be accurate in predicting turn-on and turn-off transients  相似文献   
3.
The purpose of this study was a detailed characterization of Shewanella sp. O23S, a strain involved in arsenic transformation in ancient gold mine waters contaminated with arsenic and other heavy metals. Physiological analysis of Shewanella sp. O23S showed that it is a facultative anaerobe, capable of growth using arsenate, thiosulfate, nitrate, iron or manganite as a terminal electron acceptor, and lactate or citrate as an electron donor. The strain can grow under anaerobic conditions and utilize arsenate in the respiratory process in a broad range of temperatures (10–37 °C), pH (4–8), salinity (0%–2%), and the presence of heavy metals (Cd, Co, Cr, Cu, Mn, Mo, Se, V and Zn). Under reductive conditions this strain can simultaneously use arsenate and thiosulfate as electron acceptors and produce yellow arsenic (III) sulfide (As2S3) precipitate. Simulation of As-removal from water containing arsenate (2.5 mM) and thiosulfate (5 mM) showed 82.5% efficiency after 21 days of incubation at room temperature. Based on the obtained results, we have proposed a model of a microbially mediated system for self-cleaning of mine waters contaminated with arsenic, in which Shewanella sp. O23S is the main driving agent.  相似文献   
4.
Numerical modeling of electrostatic discharge generators   总被引:9,自引:0,他引:9  
The discharge current and the transient fields of an electrostatic discharge (ESD) generator in the contact mode are numerically simulated using the finite-difference time-domain method. At first the static field is established. Then the conductivity of the relay contact is changed, which initiates the discharge process. The simulated data are used to study the effect of design choices on the current and fields. They are compared to measured field and current data using a multidecade broadband field and current sensors. The model allows accurate prediction of the fields and currents of ESD generators, thus it can be used to evaluate different design choices.  相似文献   
5.
Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.  相似文献   
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Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach  相似文献   
9.
Simple design maxims to restrict slot dimensions in enclosure designs below a half-wave length are not always adequate for minimizing electromagnetic interference (EMI). Complex interactions between cavity modes, sources, and slots can result in appreciable radiation through nonresonant length slots. The finite-difference time domain (FDTD) method can be employed to pursue these issues with adequate modeling of thin slots. Subcellular FDTD algorithms for modeling thin slots in conductors have previously been developed. One algorithm based on a quasistatic approximation has been shown to agree well with experimental results for thin slots in planes. This FDTD thin-slot algorithm is compared herein with two-dimensional (2-D) moment method results for thin slots near corners and plane wave excitation. FDTD simulations are also compared with measurements for slots near an edge of a cavity with an internal source  相似文献   
10.
The application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for DC power-bus modeling in high-speed digital designs is detailed. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of the Green's functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for the Green's functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric constant to a desired frequency. Several power-bus design issues, such as surface mount decoupling and power-plane segmentation, were investigated using the modeling approach. The results and discussions illustrate the application of the method to DC power-bus design for printed circuit and multi-chip module substrates  相似文献   
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