A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Is the Hubble Constant Scale-Dependent?

An exact determination of the Hubble constant remains one of key problems in cosmology for almost a century. However, its modern values derived by various methods still disagree from each other by almost 10%, larger values being obtained by measurements at relatively small distances (e.g., by Cepheid stars as standard candles), while smaller values are characteristic of the methods associated with huge spatial scales (e.g., from the analysis of cosmic microwave background fluctuations). A reasonable way to resolve this puzzle is to assume that the Hubble constant is inherently scale-dependent. This idea seems to be particularly attractive in the light of the latest observational results on the early-type galaxies, where dark matter halos are almost absent. Therefore, an average contribution of the irregularly distributed dark matter to the rate of the cosmological expansion should be substantially different at various spatial scales. As follows from rough estimates, the corresponding variation of the Hubble constant can be about 10% and even more, which well explains the spread in its values obtained by different methods.     

Thickness dependence of stress-induced leakage currents in siliconoxide

The thickness dependence of high-voltage stress-induced leakage currents (SILC's) has been measured in oxides with thicknesses between 5 and 11 nm. The SILC's were shown to be composed of two components: a transient component and a DC component. Both components were due to trap-assisted tunneling processes. The transient component was caused by the tunnel charging and discharging of the stress-generated traps near the two interfaces. The DC component was caused by trap-assisted tunneling completely through the oxide. The thickness, voltage, and trap density dependences of both of these components were measured. The SILC's will affect data retention in electrically erasable programmable read-only memories (EEPROM's) and the DC component was used to estimate to fundamental limitations on oxide thicknesses     

Properties of high-voltage stress generated traps in thin siliconoxide

It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps     

Extrapolation of high-voltage stress measurements to low-voltageoperation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2×10^-5 C/cm² to 6 C/cm² by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation     

Crystalline properties of multiple BP-Si layers grown on silicon substrate

In BP (100) epitaxially grown on Si (100), a high density of defects existed in the early growth layer of the BP less than 100 nm from the Si interface. The BP layer then had a uniform distribution of defects over the high density defect layer. The Si (100) grown on the BP (100) had a uniform distribution of defects. As multiple BP-Si layers were grown, the crystalline quality gradually degraded. The crystalline quality of the underlying BP layer strongly influenced the Si epitaxial layer.     

Parametric optimization of a power measuring instrument

Mathematical and simulation models of an analog-to-digital power measuring instrument are presented. Examples of the use of the simulation model for choosing the optimum parameters of the instruments are given. __________ Translated from Izmeritel’naya Tekhnika, No. 10, pp. 51–54, October, 2007.     

舰船重点部位腐蚀监测系统研究

根据舰船重点部位的腐蚀环境、特点和机理,对比分析了常用监测技术原理、方法和局限性,确定联合采用电化学噪声技术和传感器技术,研制出了集"测量、采集和存储"于一体的舰船腐蚀监测系统,其数据采集频率可高达10 Hz、电位测量范围为-4 000~4 000 m V,精度达到1 m V。     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Defect generation in silicon

Defects can be generated in silicon during device processing. It is shown that the quality of the finish on the edges and reverse side of the wafer are important in determining the defect density of the crystal after processing. Wafers with defect densities of the order of 10² per sq cm before processing, have had defect densities of the order of 10⁶ per sq cm after processing if the work damage was not removed from the back side of the wafers, and defect densities of the order of 10² per sq cm if the work damage had been removed from the back side. Chips on the edges of the wafers are shown to lead to slip lines of dislocations propagating in toward the center of the wafer. This generation of defects during thermal processing appears to be related to a stress-relief mechanism taking place at elevated temperatures. The thermally generated defects have been observed to lower the lifetime in bulk silicon and to cause increases in the leakage current of individual diodes in integrated circuits.