A formal approach to designing delay-insensitive circuits

Summary A method for designing delay-insensitive circuits is presented based on a simple formalism. The communication behavior of a circuit with its environment is specified by a regular expression-like program. Based on formal manipulations this program is then transformed into a delay-insensitive network of basic elements realizing the specified circuit. The notion of delay-insensitivity is concisely formalized. Jo C. Ebergen received his Master's degree in Mathematics from Eindhoven University of Technology in 1983. From 1983 until 1987 he has been working as a researcher at the Centre for Mathematics and Computer Science in Amsterdam in the area of VLSI design. In 1987, he received his Ph.D. degree from Eindhoven University of Technology. Currently, he is assistant professor at the University of Waterloo. His main research interests are programming methodology, parallel computations, and delay-insensitive circuit design. Dr. Ebergen is a member of ACM and EATCS.The research reported in this article was carried out while the author was working at CWI (Centre for Mathematics and Computer Science) in Amsterdam     

Modeling and comparing CMOS implementations of the C-element

Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions     

Design and analysis of delay-insensitive modulo-N counters

Various delay-insensitive circuits for modulo-N counters are formally derived and analyzed. Modulo-N counters are used in many circuit designs and have a simple specification, but allow for a surprising variety of decompositions into networks of basic components. We present three decompositions in detail. Along the way we explai our correctness criteria and show to analyze the area complexity and response time of each decomposition. Our final decomposition for the modulo-N counter has optimal area complexity of (logN) and optimal response time of (1).     

Response-time properties of linear asynchronous pipelines

One of the potential advantages of asynchronous circuits is that they can be optimized for average-case performance rather than worst-case performance. The performance analysis of asynchronous circuits, however, is more challenging than that of synchronous circuits because of the absence of a clock. We discuss some performance measures of special asynchronous networks, viz., response-time properties of asynchronous pipelines with various handshake communications. The response times of a pipeline are the delays between requests and succeeding acknowledgments for the first cell. We derive simple formulas for the bound on worst-case response time and average-case response time of such pipelines using a variable-delay model, where delays may vary between a lower and upper bound. The properties are independent of any particular implementation of the cells of the pipeline. The formulas give insight into the role of each parameter and allow a quick back-of-the-envelope prediction of the performance of an asynchronous pipeline