Breakdown voltage improvement in strained InGaAlAs/GaAs FETs

GaAs MESFETs with a surface layer of pseudomorphic InGaAlAs have been fabricated. The compressive strain and wide bandgap in the InGaAlAs layer reduce the impact ionization rate in this layer and improve the breakdown voltage of the device. A 1 μm×75 μm gate device with the pseudomorphic surface layer showed an improvement in gate-to-drain breakdown of over 55% and an improvement in channel breakdown of 50% as compared to a similar device without the pseudomorphic layer. Both devices had a peak transconductance of about 190 mS/mm and a saturation current of about 265 mA/mm     

Theoretical analysis of the breakdown voltage in pseudomorphicHFETs

In this paper a two-dimensional (2-D) model based on a solution to the moments of the Boltzmann transport equation is used to study breakdown in pseudomorphic Heterojunction Field Effect Transistors (HFETs). The effects of the energy conservation equation and the space charge effects of generated carriers are studied in the model. The model is then used to study breakdown in GaAs channel and In_0.53Ga _0.47As channel HFETs. The model shows that impact ionization breakdown in these structures is dominated by generation in two regions: (1) the high field region near the corner of the gate, and (2) the channel near the top heterojunction. Next, the effect of a thin pseudomorphic layer, which has a high threshold energy for impact ionization, is studied. This layer is shown to significantly improve the breakdown. voltage of the HFET if used properly. Finally the effects of doping on breakdown voltage of these HFETs are studied. This study shows that increased doping can improve the maximum estimated output power of these devices     

Manufacturable GaAs VFET for power switching applications

We have developed a manufacturable process to fabricate high performance GaAs vertical field effect transistors (VFET's). Our process uses ion implantation to form the gate as opposed to previous VFET processes, which used epitaxial regrowth or angled evaporation. In this process, trenches 1.2 μm wide by 0.6 μm deep with a period of 2.4 μm are formed by reactive ion etch (RIE) then the gate region is formed at the bottom of the trench by Ar/C ion co-implantation. Current handling capability of these devices exceeds 200 A/cm² with a specific on-resistance of 0.25 mΩ-cm² and calculated delay times of 13.9 ps     

Epitaxial Pb(Zr,Ti)O<Subscript>3</Subscript> Capacitors on Si by Liquid Delivery Metalorganic Chemical Vapor Deposition

La_0.5Sr_0.5CoO₃/Pb(Zr_xTi_1–x)O₃/La_0.5Sr_0.5CoO₃ capacitors have been successfully fabricated by liquid delivery metalorganic chemical vapor deposition on Si wafers using SrTiO₃ thin layer (20 nm) as a template. Zr(dmhd)₄ in tetrahydrofuran was used as Zr precursor for compatible thermal behavior with Pb(thd)₂ and Ti(OiPr)₂(thd)₂ precursors. The dependence of the ferroelectric film composition on the precursor mixing ratio and growth temperature has been systematically studied by Rutherford Backscattering (RBS). Ferroelectric and piezoelectric properties at the composition close to morphotropic phase boundary region (Pb(Zr_0.5Ti_0.5)O₃) have been investigated for application in nonvolatile ferroelectric random access memories and microelectromechanical system (MEMS). These capacitors show desirable ferroelectric properties, which proves that this approach is very promising for both fundamental study and potential applications. The changes of spontaneous polarization (P_s) and piezoelectric coefficient (d₃₃) with Ti/(Zr + Ti) ratio are also presented and compared with theoretical values.     

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In_0.5Al_0.5As/In_0.5Ga_0.5 As HEMTs have been grown metamorphically on GaAs substrates oriented 6° off (100) toward (111)A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-μm gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 μm×3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V_d=1 V     

Crystalline oxide-based devices on silicon substrates

We have developed a process to grow epitaxial SrTiO₃ (STO) on Si. This STO/Si substrate can then be used as a pseudo substrate for the further deposition of many other oxides that are closely lattice matched to STO. The STO is grown by molecular-beam epitaxy (MBE) with a subsequent oxide layer deposited either by MBE or sol-gel deposition. The pseudo substrate has been used to demonstrate ferroelectric devices and piezoelectric devices. Ferroelectric capacitors using epitaxial BaTiO₃ (BTO) show a memory window of 0.5 V; however, the retention time for these devices is short because of the depolarization field caused by the silicon-oxide interface layer used to improve the band alignment of the BTO/Si interface. Surface acoustic wave (SAW) resonators using epitaxial Pb(Zr,Ti)O₃ show excellent response with a coupling coefficient of 4.6% and a velocity of 2,844 m/s.