Home Automation Using Augmented Reality (HAAR)

Wireless Personal Communications - The development of Smart Home Controllers has seen rapid growth in recent years, especially for smart devices, that can utilize the Internet of Things (IoT)....     

Power characteristics of inductive interconnect

The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.     

Joint estimation of the channel and I/Q imbalance for two-way relay networks

In modern day communication systems, the massive MIMO architecture plays a pivotal role in enhancing the spatial multiplexing gain, but vice versa the system energy efficiency is compromised. Consequently, resource allocation in-terms of antenna selection becomes inevitable to increase energy efficiency without having any obvious effect or compromising the system spectral efficiency. Optimal antenna selection can be performed using exhaustive search. However, for a massive MIMO architecture, exhaustive search is not a feasible option due to the exponential growth in computational complexity with an increase in the number of antennas. We have proposed a computationally efficient and optimum algorithm based on the probability distribution learning for transmit antenna selection. An estimation of the distribution algorithm is a learning algorithm which learns from the probability distribution of best possible solutions. The proposed solution is computationally efficient and can obtain an optimum solution for the real time antenna selection problem. Since precoding and beamforming are also considered essential techniques to combat path loss incurred due to high frequency communications, so after antenna selection, successive interference cancellation algorithm is adopted for precoding with selected antennas. Simulation results verify that the proposed joint antenna selection and precoding solution is computationally efficient and near optimal in terms of spectral efficiency with respect to exhaustive search scheme. Furthermore, the energy efficiency of the system is also optimized by the proposed algorithm, resulting in performance enhancement of massive MIMO systems.

     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Resistive Power in CMOS Circuits

Interconnect resistance dissipates a portion of the total transient power in CMOS circuits. Conduction losses increase with larger interconnect resistance. It is shown in this paper that these losses do not add to the total power dissipation of a CMOS circuit through I ² R losses. Interconnect resistance can, however, increase the short-circuit power of both the driver and load gates.     

Asynchronous switching for low-power networks-on-chip

Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports α_data is less than Aα_c+Bα_clk. Closed form expressions for power dissipation of different network topologies are provided for both synchronous and asynchronous switching. The expressions are technology independent and are used for power estimation. Asynchronous switching is compared with synchronous switching for different network densities N/L_cXL_c. The area of the asynchronous switch is 50% greater than the area of the synchronous switch. However, the power dissipation of asynchronous switching decreased by up to 70.8% as compared to the power dissipation of the conventional synchronous switching for Butter-Fly Fat Tree (BFT) topology. Asynchronous switching is more efficient in CLICHE topology than in both BFT and Octagon topologies achieving higher power reduction 75.7%. Asynchronous switching becomes more efficient as technology advances and network density increases. A reduction in power dissipation reaches 82.3% for 256 IPs with the same chip size. Even with clock gating, asynchronous switching achieves significant power reduction 77.7% for 75% clock activity factor.     

Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.