50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system     

Parallel coupled-line bandpass filter with branch-line shape for g-band frequency

A parallel coupled-line planar bandpass filter (BPF) with branch-line shape using coplanar waveguide technology on GaAs substrate is presented. The unit parallel coupled-line BPF utilises a parallel coupled-line resonator with an open-ended stub which has suppression response of spurious band. Four unit parallel coupled-line BPFs are integrated with branch-line shape and open-circuit stubs on input and output ports are also integrated for improvement of rejection performance. The proposed fourth-order filter was fabricated on GaAs substrate with dielectric thickness of 50 m and gold thickness of 1.2 mum. The fabricated fourth-order BPF shows a 3 dB bandwidth from 177 to 209 GHz frequency range with insertion loss of 6.5 dB, rejection of 38 dB and return loss better than 12 dB. It has a high resolution fractional bandwidth of 17%.     

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.     

50 nm metamorphic GaAs and InP HEMTs

This paper reviews some of the recent work at the Nanoelectronics Research Centre at the University of Glasgow on the optimisation of 50 nm metamorphic GaAs and InP HEMTs. Typical DC and RF figures of merit obtained from 50 nm metamorphic GaAs HEMTs include I_dss of 800 mA/mm, g_m of 1100 mS/mm, threshold voltage standard deviation of 5 mV across a 25 mm × 25 mm area, f_T of 440 GHz and f_max of 400 GHz, all at a drain bias of 1.0 V. To our knowledge, these are the highest operating frequency GaAs-based transistors to date. At V_d = 0.8 V and V_g = − 0.6 V, a NF_min and G_ass of 0.7 dB and 13 dB respectively at 26 GHz have been demonstrated.For similar geometry InP HEMTs, DC and RF figures of merit are the following: I_dss of 900 mA/mm, g_m of 1600 mS/mm, f_T of 550 GHz, f_max of 440 GHz, and NF_min and G_ass of 0.9 dB and 14 dB respectively at 26 GHz. The highest performance 50 nm HEMTs reported to date. Using these technologies, single stage MMMICs with gain of at least 7 dB and a return loss of better than − 5 dB across a 24 GHz bandwidth from 71 GHz to 95 GHz have been realised. Noise figure of 2.5 dB and associated gain of 7.3 dB at 90 GHz have been achieved with a DC power consumption of 20 mW.     

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.     

On-wafer determination of impedance of planar 100 GHz double slotantenna

An on-wafer measurement strategy for determining the driving point impedance of a planar 100 GHz double slot antenna is presented. The technique is verified by comparison with a theoretical determination of the antenna impedance