Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.     

PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

With the de facto transformation of technology into nano-technology, more and more functional components can be embedded on a single silicon die, thus enabling high degree pipelining operations such as those required for multimedia applications. In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with multiple processors, on-chip memories, standard peripherals, and other functional blocks. The communication between these IP blocks is becoming the dominant critical system path and performance bottleneck of system-on-chip designs. Network-on-chip architectures, such as Virtual Channel (2004), Black-bus (2004), Pirate (2004), AEthereal (2005), and VICHAR (2006) architectures, emerged as promising solutions for future system-on-chip communication architecture designs. However, these existing architectures all suffer from certain problems, including high area cost and communication latency and/or low network throughput. This paper presents a novel network-on-chip architecture, Pipelining Multi-channel Central Caching, to address the shortcomings of the existing architectures. By embedding a central cache into every switch of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating the effect of head-of-line and deadlock problems and achieving higher network throughput and lower communication latency without paying the price of higher area cost. Experimental results showed that the proposed architecture exhibits both hardware simplicity and system performance improvement compared to the existing network-on-chip architectures.     

Boosting the efficiency of solar cells fabricated on electromagnetic cold crucible cast multicrystalline silicon by means of hydrogen passivation

In this work the improvement of the quality of the electromagnetic cold crucible cast multicrystalline silicon (EMC) material produced by Sumitomo Sitix Co. (SCC, previously Osaka Titanium Co.) by hydrogen plasma is investigated with the final goal of realizing solar cells with the maximum posible efficiency. Two different hydrogen passivation techniques are implemented: hydrogen passivation by means of rf (radio frequency) plasma treatment and hydrogen passivation using microwave induced remote plasma treatment. By combining the oxide surface passivation and hydrogen passivation by remote plasma from the front side and by rf plasma from the back side, a significant improvement in short-circuit current, in open-circuit voltage, and in fill factor is obtained. A maximum efficiency of 16% on 2 × 2 cm² cells and of 14.5% on 10 × 10 cm² cells is achieved. This 16% efficiency is the highest ever reported on EMC multicrystalline silicon.     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells     

Recent results obtained at IMEC on multicrystalline silicon solar cells

In order to optimize the efficiency of multicrystalline silicon solar cells, the influence of specific process steps and sequences were studied. Therefore clean-room high efficiency as well as industrial screen-printed cells were fabricated. Benefits are found in choosing a substrate with lower base resistivity, using front and rear oxide passivation, using hydrogen passivation for bulk and surfaces, the use of Si₃N₄ with a double function i.e. as an anti-reflection and passivation layer and the use of mechanical V-grooving. Efficiencies of 17% are found on 4 cm² clean-room fabricated cells and 15.2% has been obtained on 100 cm² V-grooved screenprinted industrial cells.     

Gaussian pulse approximation using standard CMOS and its application for sub‐GHz UWB impulse radio

Gaussian pulse is widely used in communication systems. The true Gaussian function is not physically realizable, but it can be approximated through linear functions. This paper presents a Gaussian pulse approximation approach to generate a quasi‐Gaussian pulse by using the transient response of a CMOS inverter. The basic structure of the proposed design includes a digital variable square pulse generator, a Gaussian pulse generator and a small antenna model. The digital variable square pulse generator makes the amplitude and width of the generated quasi‐Gaussian pulse tunable. The proposed pulse generator works well for three different electrical small antenna models. The simulation results show that the generated pulse approximates the Gaussian shape very well and the radiated signal at the antennas is compliant with the Federal Communication Commission's spectral mask for the 0–960 MHz band. The simple structure of this Gaussian pulse generator lends itself to a low‐power, single‐chip UWB transceiver solution. Copyright © 2008 John Wiley & Sons, Ltd.     

Hydrogen in polycrystalline silicon solar cell material: Its role and characteristics

The role and the characteristics of hydrogen in different polycrystalline silicon material are studied in this paper. The hydrogen diffusion through the grains and the grain boundaries, and its diffusion coefficient, are investigated. Moreover, the influence of the oxygen and the carbon contents on the diffusion mechanism of hydrogen in silicon is addressed. Also, it is found that the minority carrier diffusion length of polycrystalline silicon wafers considerably improves when annealed in hydrogen at high temperatures (>1000°C). Consequently, a significant amount of oxygen is out-diffused from the bulk of the wafers.     

A Lightweight Collaborative Fault Tolerant Target Localization System for Wireless Sensor Networks

Efficient target localization in wireless sensor networks is a complex and challenging task. Many past assumptions for target localization are not valid for wireless sensor networks. Limited hardware resources, energy conservation, and noise disruption due to wireless channel contention and instrumentation noise pose new constraints on designers nowadays. In this work, a lightweight acoustic target localization system for wireless sensor networks based on time difference of arrival (TDOA) is presented. When an event is detected, each sensor belonging to a group calculates an estimate of the target's location. A fuzzyART data fusion center detects errors and fuses estimates according to a decision tree based on spatial correlation and consensus vote. Moreover, a MAC protocol for wireless sensor networks (EB-MAC) is developed which is tailored for event-based systems that characterizes acoustic target localization systems. The system was implemented on MicaZ motes with TinyOS and a PIC 18F8720 microcontroller board as a coprocessor. Errors were detected and eliminated hence acquiring a fault tolerant operation. Furthermore, EB-MAC provided a reliable communication platform where high channel contention was lowered while maintaining high throughput.     

Efficient shield insertion for inductive noise reduction in nanometer technologies

With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach.     

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.