Validity of the Parabolic Effective Mass Approximation in Silicon and Germanium n-MOSFETs With Different Crystal Orientations

This paper investigates the validity of the parabolic effective mass approximation (EMA), which is almost universally used to describe the size and bias-induced quantization in n-MOSFETs. In particular, we compare the EMA results with a full-band quantization approach based on the linear combination of bulk bands (LCBB) and study the most relevant quantities for the modeling of the mobility and of the on-current of the devices, namely, the minima of the 2-D subbands, the transport masses, and the electron density of states. Our study deals with both silicon and germanium n-MOSFETs with different crystal orientations and shows that, in most cases, the validity of the EMA is quite satisfactory. The LCBB approach is then used to calculate the values of the effective masses that help improve the EMA accuracy. There are crystal orientations, however, where the 2-D energy dispersion obtained by the LCBB method exhibits features that are difficult to reproduce with the EMA model.     

Modeling of electron mobility degradation by remote Coulomb scattering in ultrathin oxide MOSFETs

This paper presents a comprehensive, numerical model for the remote Coulomb scattering (RCS) in ultrathin gate oxide MOSFETs due to ionized impurities in the polysilicon. Using a nonlocal screening approach, the model accounts for the static screening of the scattering centers produced both by electrons in the channel and in the polysilicon. Electron mobility is then calculated using a relaxation time approximation that consistently accounts for intersubband transitions and multisubband transport. Our results indicate that neglecting the screening in the polysilicon and making use of the Quantum Limit (QL) approximation can lead to a severe underestimate of the RCS limited electron mobility, thus hampering the accuracy of the predictions reported in some previous papers on this topic. Using our model, we discuss the oxide thickness dependence of the electron mobility in ultrathin gate oxide MOSFETs and the possible benefits in terms of RCS limited mobility leveraged by the use of high K dielectrics.     

Injection efficiency of CHISEL gate currents in short MOS devices:physical mechanisms, device implications, and sensitivity totechnological parameters

This paper analyzes MOSFET gate currents in the so-called channel initiated secondary electron injection regime (CHISEL). A Monte Carlo model of the phenomenon is validated and then extensively used to explore CHISEL scaling laws. Results indicate that, compared to conventional channel hot electron injection (CHE), CHISEL exhibits a weaker dependence on channel length and a larger sensitivity to short channel effects. These results are confirmed experimentally and exhaustively explained with the help of simulations; furthermore, some of their possible detrimental consequences on the programming efficiency of CHISEL based flash cells are analyzed. Finally, the impact of channel doping, oxide thickness, and junction depth on CHISEL efficiency has been explored, and guidelines to maintain high injection efficiency in short devices are derived     

Mobility Enhancement in Strained $n$ -FinFETs: Basic Insight and Stress Engineering

This paper presents both analytical models and Monte Carlo simulations concerning strain engineering in $n$-type silicon FinFETs. Our analysis identifies the stress configurations and the physical mechanisms able to produce a significant stress-induced mobility enhancement and provides the insight necessary for device optimization. We first derive analytical expressions for the stress-induced changes of the subband minima and of the transport masses, which clearly identify the stress components leading to mobility improvements. Then, we present multisubband Monte Carlo mobility simulations, which confirm the potentials for remarkable stress-induced mobility enhancements in $n$ -FinFETs.      

Damage generation and location in n- and p-MOSFETs biased in theSubstrate-Enhanced Gate Current regime

This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n⁺-poly n-MOSFETs and p⁺-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel     

Nonscaling of MOSFET's linear resistance in the deep submicrometerregime

This paper investigates the scaling properties of deep submicron MOSFET's and shows that, while in a wide range of channel lengths they can be represented as composed by a scaling intrinsic and a nonscaling parasitic part, this picture does no longer hold for shorter transistors. A nonscaling of the total resistance R_TOT=[V_DS/I_DS] of short devices is observed, and its impact on parasitic resistances and effective channel length extraction is discussed. A possible explanation is suggested in relation to the two-dimensional substrate doping redistribution linked to reverse-short-channel effects     

On interface and oxide degradation in VLSI MOSFETs. I. Deuteriumeffect in CHE stress regime

This paper analyzes in detail the generation of interface states (N_it) and stress-induced leakage current (SILC) during channel hot electron (CHE) stress experiments in the context of a possible hydrogen/deuterium (H/D) isotope effect. Our results show that N_it generation is related to the hydrogen release (HR) at the Si-SiO₂ interface at relatively high V_G where a large isotope effect is found. Instead, for gate voltages (V_G) favorable for hot hole injection (HHI) the N_it creation becomes a unique function of hole fluence and the isotope effect disappears. In the studied stress conditions, we found no experimental evidence supporting a causal relation between SILC generation and HR because no isotope effect is observed even when the corresponding N_it measurements reveal a very different D/H release rate. Similar to N_it generation, we found that SILC becomes a unique function of hole fluence at low stress V_G. Relevant implications and extensions of these results to the Fowler-Nordheim (FN) tunneling stress conditions are discussed in Pt. II     

Revised stability analysis of the nonlinear Poisson scheme in self-consistent Monte Carlo device simulations

In this paper, the stability of self-consistent Monte Carlo (MC) device simulations is revised by developing a model that extends the existing ones by accounting for the effect of a carrier diffusion. Both the linear and the nonlinear Poisson schemes have been considered. The analysis of the linear Poisson scheme reveals that, consistently with the available model, the time step between two Poisson solutions must be short compared to a factor proportional to the scattering rate. On the other hand, it has been found that, contrary to the available stability models, the nonlinear Poisson scheme requires long time steps in order to provide stable simulations. For this reason, the nonlinear scheme is advantageous when considering steady-state simulations. The model predictions have been verified by comparison with MC simulations implementing both schemes.     

Hot-carrier-induced alterations of MOSFET capacitances: aquantitative monitor for electrical degradation

In this paper, combined gate-to-channel (C_GSD) and gate-to-bulk (C_GB) capacitance measurements are used in order to extract quantitative information about hot-carrier degradation in MOS transistors. An analytical model, explaining the results of accelerated degradation experiments, is presented to establish a simple relationship between C_GSD and C_GB changes and the stress-induced charges Q_ox and Q_it trapped in the oxide or in interface states, respectively. A method, validated by means of two-dimensional (2-D) numerical simulations, is proposed to determine Q_ox and Q_it directly from the measured capacitances, and is applied to experimental data. The new technique considerably improves the capabilities of previous capacitive methods because it can yield a quantitative determination of Q_ox and Q_it