Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology

CoHub, a coherency hub ASIC, provides a cost-effective way to extend a glueless two-node chip-multithreading system to a four-node system without changes to the processor. The four-node, 256-thread system achieves near-linear scaling of performance with thread count on transaction-processing workloads. Time-to-market pressure, 800-MHz operation, and a six-stage pipeline were among the constraints that shaped CoHub's design.     

The effect of propagation delay uncertainty on the speed oftime-of-flight digital optoelectronic circuits

Time-of-flight synchronization is a new digital design methodology for optoelectronics that eliminates latches, allowing higher clock rates than alternative timing schemes. Synchronization is accomplished by precisely balancing connection delays. Circuits use pulse-mode signaling and clock gates to restore pulse timing. Many effective pipeline stages are created within combinational logic without extra hardware bounding the stages. Time-of-flight design principles are applicable to packet routing and sorting processors for optical interconnection networks. Circuits are unique because the clock rate is limited primarily by imprecision in propagation delay rather than absolute delay, as in circuits with latches. We develop a general model of delay uncertainty and focus on the effect that static and dynamic uncertainty accumulated over circuit paths has on the minimum feasible clock period. We present a method for traversing the circuit graph representation of a time-of-flight circuit to compute arrival time uncertainty at each pulse interaction point. Arrival time uncertainties give rise to pulse width and overlap constraints. From these constraints we formulate a constrained minimization to find the minimum clock period. We demonstrate our method on circuits implemented with 2×2 electro-optic switches and optical waveguides and find the electronic component of path uncertainty frequently limits speed     

Placement of clock gates in time-of-flight optoelectronic circuits

Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.     

Packet synchronization for synchronous optical deflection-routedinterconnection networks

Deflection routing resolves output port contention in packet switched multiprocessor interconnection networks by granting the preferred port to the highest priority packet and directing contending packets out other ports. When combined with optical links and switches, deflection routing yields simple bufferless nodes, high bit rates, scalable throughput, and low latency. We discuss the problem of packet synchronization in synchronous optical deflection networks with nodes distributed across boards, racks, and cabinets. Synchronous operation is feasible due to very predictable optical propagation delays. A routing control processor at each node examines arriving packets and assigns them to output ports. Packets arriving on different input ports must be bit wise aligned; there are no elastic buffers to correct for mismatched arrivals. “Time of flight” packet synchronization is done by balancing link delays during network design. Using a directed graph network model, we formulate a constrained minimization problem for minimizing link delays subject to synchronization and packaging constraints. We demonstrate our method on a ShuffleNet graph, and show modifications to handle multiple packet sizes and latency critical paths