Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Simple and efficient modeling of EPROM writing

A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 μm     

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO₂ dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance     

Revised stability analysis of the nonlinear Poisson scheme in self-consistent Monte Carlo device simulations

In this paper, the stability of self-consistent Monte Carlo (MC) device simulations is revised by developing a model that extends the existing ones by accounting for the effect of a carrier diffusion. Both the linear and the nonlinear Poisson schemes have been considered. The analysis of the linear Poisson scheme reveals that, consistently with the available model, the time step between two Poisson solutions must be short compared to a factor proportional to the scattering rate. On the other hand, it has been found that, contrary to the available stability models, the nonlinear Poisson scheme requires long time steps in order to provide stable simulations. For this reason, the nonlinear scheme is advantageous when considering steady-state simulations. The model predictions have been verified by comparison with MC simulations implementing both schemes.     

0.15-μm buried-channel p-MOSFETs with ultrathin boron-dopedepitaxial Si layer

We demonstrated silicon MOSFETs with a counter-doped ultrathin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with boron with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, and so it is easy to adjust the threshold voltage of the buried-channel p-MOSFETs with n-type polysilicon gates. It was confirmed that choosing an ultrathin epitaxial layer at 10 nm leads to suppression of the short-channel effects in buried-channel p-MOSFETs with gate length down to 0.15 μm, while maintaining an appropriate value of threshold voltage     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.     

Stability of self-consistent Monte Carlo Simulations: effects of the grid size and of the coupling scheme

In this paper, the authors show that the grid spacing affects the stability of self-consistent Monte Carlo device simulations. An analytical model is derived to describe this effect. Guidelines for the choice of the grid size are provided, showing that, when the linear Poisson scheme is used, source/drain extensions with doping level as high as 10/sup 20/ cm/sup -3/ require grid spacing lower than 1 nm in order to have stable simulations. On the other hand, the nonlinear coupling scheme does not impose any constraint, provided that the time between two solutions of the Poisson equation is so long that each solution can be considered as a stationary solution of the Boltzmann transport equation.     

Latch-up testing in CMOS IC's

Experimental data obtained by testing CMOS commercial ICs for latchup by means of automatic test equipment are presented. The results unambiguously show that latchup resistance is strongly influenced by interactions among complex structures within the circuit that are overlooked by widely used testing procedures. In particular, it is shown that both multiple pin excitation and static current loading can significantly decrease the component latchup resistance because of effects taking place within the semiconductor as well as through metal lines