Laparoscopic distal resection of the pancreas with the preservation of the spleen

Management of the pancreatic diseases is still a challenge to the laparoscopic technique. Some experience has been gained in the laparoscopic exploration of the pancreas and staging in cancer. Anatomically the accessibility of the distal pancreas provides the laparoscopic approach technically feasible. Patient and method: A case of insuloma in the tail of the pancreas is presented, where distal pancreatic resection was performed laparoscopically with the preservation of the spleen. In a 55 years old female patient with typical clinical symptoms of hyperinsulinism CT identified a 3 cm large solid tumor in the tail of the pancreas. Complete mobilization of the distal pancreas was enhanced by the use of an ultrasonic dissector (UltraCision). The pancreas is detached from the splenic hilum after dividing the spleen vessels. The pancreas is transected proximally by laparoscopic linear stapler. Preservation of the short gastric vessels provides the necessary blood supply of the spleen following division of the splenic artery and vein. Thus removal of the spleen is not a necessary step in this procedure. The operation was carried out within 4.5 hours. Postoperative course was uneventful, the patient left the hospital on the 5th postoperative day. Advantages of the procedure were the earlier mobilization and shorter recovery time, less postoperative pain. The procedure can be safely performed with a good experience in both pancreatic and laparoscopic surgery.     

Circuit and microarchitectural techniques for reducing cache leakage power

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. As feature sizes shrink, the dominant component of this power consumption will be leakage. However, during a fixed period of time, the activity in a data cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large data caches by putting the cold cache lines into a state preserving, low-power drowsey mode. In this paper, we investigate policies and circuit techniques for implementing drowsy data caches. We show that with simple microarchitectural techniques, about 80%-90% of the data cache lines can be maintained in a drowsy state without affecting performance by more than 0.6%, even though moving lines into and out of a drowsy state incurs a slight performance loss. According to our projections, in a 70-nm complementary metal-oxide-semiconductor process, drowsy data caches will be able to reduce the total leakage energy consumed in the caches by 60%-75%. In addition, we extend the drowsy cache concept to reduce leakage power of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. In order to enable drowsy instruction caches, we propose a technique called cache subbank prediction, which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low-leakage drowsy mode. This prediction technique reduces the negative performance impact by 78% compared with the no-prediction policy. Our technique works well even with small predictor sizes and enables a 75% reduction of leakage energy in a 32-kB instruction cache.     

Tumors of the papilla of Vater--diagnostic and therapeutic dilemmas

Benign and malignant tumors of papilla Vateri are rare diagnoses in the endoscopic practice. Sixteen patients with benign and 22 cases of malignant tumors are presented. In all of them endoscopic cholangiopancreatography with or without papillotomy followed by biopsy and operation in 13 cases was performed. Biopsy confirmed the endoscopy in 71%. Adenomyosis, supposed by endoscopy was proved by repeated histology in only 2/9 cases although invasive component of the tumor was found in 3/9 patients at operation underlying precancerous nature of this entity. Among 5 cases of villous adenoma one developed malignant alterations during 4 years of follow-up. Biopsy was not more effective after papillotomy than without it, and 5-7 days of delay for recovery of thermic lesion did not ameliorate success rate of histology. For malignant diseases surgical therapy should be considered if staging of tumor and general condition of the patient permits. In unresectable cases endoscopic palliation (papillotomy or polypectomy with or without drainage) can increase survival. In patients with benign tumors operative endoscopy followed by regular ultra-sonography and endoscopy seems to be necessary.     

Pancreatic pseudocysts associated with chronic pancreatitis--early and late results of 1367 operations

The authors hereby review the data of 1367 operations for pancreatic pseudocysts. The surgical procedures of choice in particular pancreatic pathologies are analysed in the light of early morbidity and mortality, as well as long term follow-up results. The best operations for pancreatic pseudocysts have been the internal drainage procedures, which resolve the pathological alterations without the necessity of pancreatic resection. The treatment of chronic pancreatitis may require combined surgical procedure, such as cysto-Wirsungo-gastrostomy. The pancreatic resections performed for the treatment of small pseudocysts in the pancreatic head have been superseded by the less invasive blunt, forced cysto-duodenostomies, representing better results secondary to the smaller perioperative risk for the patient. The cyst-to-stomach and cyst-to-duodenum internal drainage techniques are just as effective, but with shorter operation time, than the Roux-en-Y cysto-jejunostomies.     

A case of unusual complication of diaphragmatic herniation of transverse colon following transhiatal esophagectomy

The authors report a rare complication observed after transhiatal esophagus extirpation performed for esophageal cancer. In this case the transverse colon herniated into the pleural cavity through the esophageal hiatus. Herniation completed on the 6.th. postoperative day and caused mechanical ileus. In the first few postoperative days, radiology pointed to a basal pulmonal infiltrate, later it resembled relaxation of the diaphragm, which was rather misleading. Recognition of the real situation was possible only on the 6.th.postoperative day. The patient was reoperated and the pathological state could be reversed. The esophageal hiatus was reconstructed. In the opinion of the authors the complication may have developed partly due to the opening of the left pleural cavity in the course of extrathoracal esophagectomy, and partly to the fact that the spleen was removed during operation. The outcome after reoperation was uneventful. The authors consider this as a rather rare and instructive case.     

The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V/sub dd/. However, there is no fundamental reason why designs cannot operate over a much larger voltage range: from full V/sub dd/ to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that, for subthreshold supply voltages, leakage energy becomes dominant, making "just-in-time computation" energy-inefficient at extremely low voltages. Hence, we introduce the existence of a so-called "energy-optimal voltage" which is the voltage at which the application is executed with the highest possible energy efficiency and below which voltage scaling reduces energy efficiency. We derive an analytical model for the energy-optimal voltage and study its trends with technology scaling and different application loads. Second, we compare several different low-power approaches including MTCMOS, standard DVS, and the proposed Insomniac (extended DVS into subthreshold operation). A study of real applications on commercial processors shows that Insomniac provides the best energy efficiency. From these results, we conclude that extending the voltage range below V/sub dd//2 will improve the energy efficiency for many processor designs.     

Automatic Performance Setting for Dynamic Voltage Scaling

The emphasis on processors that are both low power and high performance has resulted in the incorporation of dynamic voltage scaling into processor designs. This feature allows one to make fine granularity tradeoffs between power use and performance, provided there is a mechanism in the OS to control that tradeoff. In this paper, we describe a novel software approach to automatically controlling dynamic voltage scaling in order to optimize energy use. Our mechanism is implemented in the Linux kernel and requires no modification of user programs. Unlike previous automated approaches, our method works equally well with irregular and multiprogrammed workloads. Moreover, it has the ability to ensure that the quality of interactive performance is within user specified parameters. Our experiments show that as a result of our algorithm, processor energy savings of as much as 75% can be achieved with only a minimal impact on the user experience.     

Risk factors of infected pancreatic necrosis, its microbiology and antibiotic treatment

Acute pancreatitis is associated with greater and smaller necrosis in 20% of the cases. The lethality rate of sterile and infected necrosis is 10 and 15-40%, respectively. The results of a retrospective and a prospective study in acute pancreatitis have been analyzed in this study. Twenty patients suffering from infected necrosis due to acute necrotising pancreatitis were selected into the retrospective study. They were divided into two groups: Group 1 (N = 10) survivors, Group 2 (N = 10) those who died. The fate of patients was determined by their age, the severity of pancreatitis, and the effectiveness of the operation. In a prospective study 63 patients were operated due to benign pancreatic disease with fluid collection. Microbiological samples were taken during surgery in every case. It could be stated that the Enterobacteriaceae spp. play the principal role in the infection, and the anaerobic bacteria occur sporadically. The omission of bacteriological sample taking during surgery frustrates the targeted antibiotic treatment. The blood culturing may have useful contribution. The targeted antibiotic therapy based on relevant microbiological sample taking is substantial complementary of the surgical intervention in the treatment of the inflammatory pancreatic diseases.     

Making typical silicon matter with Razor

Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit-operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and lets digital systems run correctly and robustly at the edge of minimum power consumption. Occasional heavyweight computations may fail and require additional time and energy for recovery, but the optimized pipeline requires significantly less energy overall than traditional designs.     

Leakage current: Moore's law meets static power

Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips. Until recently, only dynamic power has been a significant source of power consumption, and Moore's law helped control it. However, power consumption has now become a primary microprocessor design constraint; one that researchers in both industry and academia will struggle to overcome in the next few years. Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink below 0.1 micron, static power is posing new low-power design challenges.