Speed superiority of scaled double-gate CMOS

Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V_DD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low V_DD < ~1 V     

The heat stability of some trypsin inhibitors in meat products with special reference to added soybean protein

Summary The heat stability of the trypsin inhibitors commonly present in meat products has been investigated. This includes the naturally occurring inhibitors in meat of serum, and some of the soybean proteins usually added to minced meat and sausages. The stability of the inhibitors are investigated both alone, and when mixed with meat and other compounds.To test the inhibitory activity two methods were used. For quantitative measurement the Kunitz method was applied. For qualitative and semiquantitative investigation of inhibitory activity the casein precipitating method ofSandvik was adapted. The latter method is mote sensitive than the first mentioned.Of the animal sera investigated in the present work the inhibitors in horse serum revealed the highest thermostability. After heating for 5 min at 100° C, the trypsin inhibitory activity was 10% of the original, while the inhibitory activity in the other animal sera investigated was lost after exposure for 5 minutes at 80–85° C. The inhibitors in the various soybean proteins were far mote stable. The heat stability was shown to be pH-dependent.The inhibitory activity of the various soybean proteins was, however, destroyed when heating was carried out in the presence of meat or meat extract at 80–85° C for 2–5 min. Substances added to the minced meat, such as starch, casein, milkpowder or skimmed milk, and spices did not have this effect on the heat stability of the soybean inhibitors. It was further shown that the factor in meat responsible for decreasing the thermostability of the trypsin inhibitors in soybeans is heat labile, it was precipitated by ammonium sulphate and was a high molecular weight compound as shown by gel chromatography.The significance of this phenomenon is discussed and a possible explanation is put forward.

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Zusammenfassung Die Hitzestabilität der üblicherweise in Fleischprodukten vorhandenen Trypsininhibitoren wurde untersucht. Dies schließt die natürlichen Vorkommen von Inhibitoren in Fleisch oder Serum ein und einiger Sojaproteine, die üblicherweise Fleischbrat und Würsten zugesetzt werden. Die Stabilität der Inhibitoren wurde sowohl für rich als such mit Fleisch und anderen Verbindungen untersucht. Um die Hemmaktivität zu testen, wurden 2 Methoden angewendet; für quantitative Messungen die Kunitz-Methode, für qualitative und halbquantitative Untersuchungen die Casein precipitierende Sandvik-Methode, wobei die letztere Methode empfindlicher ist als die erste. Von den untersuchten tierischen Seren besaß der Inhibitor im Pferdeserum die höchste Thermostabilität. Nach 5 min Erhitzung auf 100° C war die trypsininhibitorische Wirkung nur noch 10% der ursprünglichen, wahrend die der anderen tierischen Seren nach 5 min bei 80–85° C vernichtet wurde. Die Inhibitoren der verschiedenen Sojabohnenproteine waren weit stabiler. Die Hitzestabilität ist pH-abhängig. Die inhibitorische Aktivität der verschiedenen Sojabohnenproteine wurde jedoch zerstört, wenn die Erhitzung in Gegenwart von Fleisch oder Fleischprodukten bei 80–85° C für 2–5 min ausgeführt wurde. Zu Fleischbrät zugesetzte Substanzen wie Stärke, Casein, Milch- oder Magermilchpulver und Gewürze haben keinen EinfluB auf die Hitzestabilität des Sojabohneninhibitors. Es wurde weiter gezeigt, daß der Faktor, der in Fleisch für die Abnahme der Thermostabilität des Trypsininhibitors in Sojabohnen verantwortlich ist, hitzelabil ist; er wurde durch Ammoniumsulfat ausgefällt und wies ein hohes Molekulargewicht, belegt durch Gelchromatographie, auf. Die Signifikanz dieser Phenomene wird diskutiert und eine mögliche Erklärung dafür gegeben.

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This work was supported by a grant from the Agricultural Research Council of Norway.     

Extremely scaled double-gate CMOS performance projections,including GIDL-controlled off-state current

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n⁺ and p⁺ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p⁺ -gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits     

Physical insights regarding design and performance of independent-gate FinFETs

Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure.     

DICE: A Beneficial Short-Channel Effect in Nanoscale Double-Gate MOSFETs

Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve nanoscale DG CMOS speed substantially.     

Monitoring hot-electron-induced degradation of floating-body SOIMOSFETs

A simple model relating the hot-electron-controlled device lifetime of floating-body SOI MOSFETs to the body voltage is discussed. The model is derived from the familiar relationship between the device lifetime and the substrate current of bulk MOSFETs, a relationship that cannot be measured directly in floating-body MOSFETs. The model, which allows quick estimation of the device lifetime from body-voltage measurements, is supported by measurements of hot-electron-induced degradation of floating-body SOI MOSFETs fabricated using SIMOX substrates     

CMOS image sensors: electronic camera-on-a-chip

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

Compression stress–strain and creep properties of the 52In–48Sn and 97In–3Ag low-temperature Pb-free solders

Lead (Pb)-free, low melting temperature solders are required for step-soldering processes used to assemble micro-electrical mechanical system (MEMS) and optoelectronic (OE) devices. Stress–strain and creep studies, which provide solder mechanical properties for unified creep-plasticity (UCP) predictive models, were performed on the Pb-free 97In–3Ag (wt.%) and 58In–42Sn solders and counterpart Pb-bearing 80In–15Pb–5Ag and 70In–15Sn–9.6Pb–5.4Cd alloys. Stress–strain tests were performed at 4.4 × 10^?5 s^?1 and 8.8 × 10^?4 s^?1. Stress–strain and creep tests were performed at ?25, 25, 75, and 100°C or 125°C. The samples were evaluated in the as-fabricated and post-annealed conditions. The In–Ag solder had yield stress values of 0.5–8.5 MPa. The values of ΔH for steady-state creep were 99 ± 14 kJ/mol and 46 ± 11 kJ/mol, indicating that bulk diffusion controlled creep in the as-fabricated samples (former) and fast-diffusion controlled creep in the annealed samples (latter). The In–Sn yield stresses were 1.0–22 MPa and were not dependent on an annealed condition. The steady-state creep ΔH values were 55 ± 11 kJ/mol and 48 ± 13 kJ/mol for the as-fabricated and annealed samples, respectively, indicating the fast-diffusion controlled creep for the two conditions. The UCP constitutive models were derived for the In–Ag solder in the as-fabricated and annealed conditions.