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1.
Yuji Fukaishi Yoshihiro Ohta Kohji Higuchi Eiji Takegami Satoshi Tomioka Kosin Chamnongthai 《Artificial Life and Robotics》2012,17(1):1-6
A robust DC?CDC converter which can covers extensive load change and also input voltage changes with one controller is needed. Then the demand to suppress output voltage change becomes still severer. We propose an approximate 2-degree-of-freedom (2DOF) digital controller which realized start-up response and dynamic load response independently. The controller makes a control bandwidth wider, and at the same time makes variations of the output voltage small at sudden changes of a load and an input voltage. In this paper, a new approximate 2DOF digital control system with additional zeros is proposed. Using the additional zeros, the second-order differential transfer characteristics between equivalent disturbances and a output voltage are realized. Therefore, the new controller makes variations of the output voltage smaller and the sudden changes of the load and the input voltage. This controller is actually implement on a DSP and is connected to the DC?CDC converter. Experimental results demonstrate that this type of digital controller can satisfy given severe specifications with low frequency sampling. 相似文献
2.
The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the performance of a system enhanced with LSI technology scaling. This is because large frequency-dependent attenuation results in poor eye-opening performance and a high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-m 28AWG cable transceiver fabricated by using 0.13-/spl mu/m CMOS technology. In this transceiver, a continuous-time post-equalizer, with recently developed no-feedback-loop high-speed analog amplifiers, can handle up to 9dB of frequency-dependent attenuation in cables and also achieve an 18-dB improvement in the attenuation (27dB total improvement) by using pre- and post-equalization techniques in combination. 相似文献
3.
Miura N. Mizoguchi D. Inoue M. Niitsu K. Nakagawa Y. Tago M. Fukaishi M. Sakurai T. Kuroda T. 《Solid-State Circuits, IEEE Journal of》2007,42(1):111-122
A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13 相似文献
4.
Fukaishi M. Nakamura S. Tajima A. Kinoshita Y. Suemura Y. Suzuki H. Itani T. Miyamoto H. Henmi N. Yamazaki T. Yotsuyanagi M. 《Solid-State Circuits, IEEE Journal of》1999,34(9):1325-1330
A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-μm CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3×2 mm2, and the power dissipation is 860 mW 相似文献
5.
Yamaguchi K. Fukaishi M. Sakamoto T. Akiyama N. Nakamura K. 《Solid-State Circuits, IEEE Journal of》2001,36(11):1666-1672
An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm2. It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5 相似文献
6.
Maeda T. Numata K. Tokushima M. Ishikawa M. Fukaishi M. Hida H. Ohno Y. 《Solid-State Circuits, IEEE Journal of》1996,31(2):240-246
This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage 相似文献
7.
Wada S. Tokushima M. Fukaishi M. Matsuno N. Yano H. Hida H. Maeda T. 《Electron Devices, IEEE Transactions on》1998,45(8):1656-1662
This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (Cfrext) of conventional Y-shaped gate HJFET's. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO2 sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al0.2Ga0.8As/In0.2Ga0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as fT=71 GHz and fmax=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced Cfrext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's 相似文献
8.
Fujii M. Numata K. Maeda T. Tokushima M. Wada S. Fukaishi M. Ishikawa M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1998,6(1):43-46
An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V 相似文献
9.
Fukaishi M. Nakamura K. Heiuchi H. Hirota Y. Nakazawa Y. Ikeno H. Hayama H. Yotsuyanagi M. 《Solid-State Circuits, IEEE Journal of》2000,35(11):1611-1618
A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s 相似文献
10.
Wada S. Furuhata N. Tokushima M. Fukaishi M. Hida H. Maeda T. 《Electron Devices, IEEE Transactions on》1998,45(6):1183-1189
This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-μm or less gate-openings with a high aspect-ratio of 3.5 in SiO 2 film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-μm voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ceext f) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-μm, T-shaped, p+-gate n-Al0.2Ga0.8As/In0.25Ga0.75 As HJFET exhibits a high gate turn-on voltage (Vf) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT=121 GHz and fmax =144 GHz is achieved due to the Cextf reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's 相似文献