排序方式: 共有21条查询结果,搜索用时 156 毫秒
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Franco Fummi Marco Boschini Xiaoming Yu Elizabeth M. Rudnick 《Journal of Electronic Testing》2001,17(3-4):321-330
Symbolic and genetic techniques are combined in a new approach to sequential circuit test generation that uses circuit decomposition, rather than the algorithmic decomposition used in previous hybrid test generators. Symbolic techniques are used to generate test sequences for the control logic, and genetic algorithms are used to generate sequences for the datapath. The combined sequences provide higher fault coverages than those generated by existing deterministic and GA-based test generators, and execution times are significantly lower in many cases. 相似文献
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Alippi C. Fummi F. Piuri V. Sami M. Sciuto D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1998,6(3):507-511
Testability analysis and test pattern generation for neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of Hopfield's networks, as the simplest example of networks with feedback loops. A behavioral error model based on finite-state machines (FSM's) is introduced. Conditions for controllability, observability and global testability are derived to verify errors excitation and propagation to outputs. The proposed behavioral test pattern generator creates the minimum length test sequence for any digital implementation 相似文献
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Giuseppe Di Guglielmo Luigi Di Guglielmo Franco Fummi Graziano Pravadelli 《Journal of Electronic Testing》2011,27(2):137-162
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of complex designs without incurring
the state explosion problem typical of the more traditional FSMs. However, traversing an EFSM can be more difficult than an
FSM because the guards of EFSM transitions involve both primary inputs and registers. This paper first analyzes the hardness
of traversing an EFSM according to the characteristics of its transitions. Then, it presents a methodology to generate an
EFSM which is easy to be traversed. Finally, it proposes a functional deterministic automatic test pattern generation (ATPG)
approach that exploits such EFSMs for functional verification. In particular, the ATPG approach joins backjumping, learning,
and constraint solving to (i) early identify possible symptoms of design errors by efficiently exploring the whole state space
of the design under verification (DUV), and (ii) generate effective input sequences to be used in further verification steps
which require to stimulate the DUV. The effectiveness of the proposed approach is confirmed in the experimental result section,
where it is compared with both genetic and pseudo-deterministic techniques. 相似文献
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Viacheslav Izosimov Giuseppe Di Guglielmo Michele Lora Graziano Pravadelli Franco Fummi Zebo Peng Masahiro Fujita 《Journal of Electronic Testing》2012,28(4):469-486
Technology shrinking and sensitization have led to more and more transient faults in embedded systems. Transient faults are intermittent and non-predictable faults caused by external events, such as energetic particles striking the circuits. These faults do not cause permanent damages, but may affect the running applications. One way to ensure the correct execution of these embedded applications is to keep debugging and testing even after shipping of the systems, complemented with recovery/restart options. In this context, the executable assertions that have been widely used in the development process for design validation can be deployed again in the final product. In this way, the application will use the assertion to monitor itself under the actual execution and will not allow erroneous out-of-the-specification behavior to manifest themselves. This kind of software-level fault tolerance may represent a viable solution to the problem of developing commercial off-the-shelf embedded systems with dependability requirements. But software-level fault tolerance comes at a computational cost, which may affect time-constrained applications. Thus, the executable assertions shall be introduced at the best possible points in the application code, in order to satisfy timing constraints, and to maximize the error detection efficiency. We present an approach for optimization of executable assertion placement in time-constrained embedded applications for the detection of transient faults. In this work, assertions have different characteristics such as tightness, i.e., error coverage, and performance degradation. Taking into account these properties, we have developed an optimization methodology, which identifies candidate locations for assertions and selects a set of optimal assertions with the highest tightness at the lowest performance degradation. The set of selected assertions is guaranteed to respect the real-time deadlines of the embedded application. Experimental results have shown the effectiveness of the proposed approach, which provides the designer with a flexible infrastructure for the analysis of time-constrained embedded applications and transient-fault-oriented executable assertions. 相似文献
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Verification of a design, based on model checking, requires the identification of a set of formal properties manually derived
from the specification of the design under verification (DUV). Such a set can include too few or too many properties. This
paper proposes to use a functional ATPG to identify missing properties and to remove unnecessary ones. In particular, the
paper refines, extends, and compares, with other symbolic approaches, a methodology to estimate the completeness of formal
properties, which exploits a functional fault model and a functional ATPG. Moreover, the same fault model and ATPG are used
to face the opposite problem of identifying useless properties, that is, properties which are in logical consequence. Logical
consequence between properties is generally examined by using theorem proving, which may require a large amount of time and
space resources. On the contrary, the paper proposes a faster approach which analyzes logical consequence by observing the
property capability of revealing functional faults. The joint use of the methodologies allows to optimize the set of properties
used for several verification sessions needed to check all design phases of an incremental design flow. 相似文献
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Ferrandi F. Fummi F. Sciuto D. Macii E. Poncino M. 《Design & Test of Computers, IEEE》1997,14(4):69-77
Because they must rely on vendor-provided test patterns, designers of core-based systems are forced to use expensive scan-based test techniques. The authors' alternative solution exploits the expressiveness of binary decision diagrams to provide test generation for the system and testability estimation and improvement of its components 相似文献
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Fummi F. Sciuto D. Silvano C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1998,6(3):502-506
This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC's) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card 相似文献
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