Breaking step: the return of asynchronous logic

Virtually all digital design is based on a synchronous approach. However, there are signs that it is beginning to hit some fundamental limitations. These limitations are described by the author. Asynchronous design as a means to overcome these limitations is then discussed. The way in which asynchronous circuits operate is discussed. The Amulet project at Manchester University, which adopted the micropipeline approach in investigating the application of asynchronous techniques to the reduction of high-performance microprocessors, is described. Future prospects for asynchronous design are briefly reviewed     

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks     

On-chip timing reference for self-timed microprocessor

A calibratable on-chip timing reference circuit has been developed to enable a self-timed microprocessor to interface to standard offchip memory and peripheral devices. The circuit exhibits several of the desirable properties of self-timed circuitry such as low power consumption and low electromagnetic interference (EMI). In addition, it is highly testable.     

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture

SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 10⁵ integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected.     

Scalable communications for a million-core neural processing architecture

The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker’s hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.     

Sparse Distributed Memory Using Rank-Order Neural Codes

A variant of a sparse distributed memory (SDM) is shown to have the capability of storing and recalling patterns containing rank-order information. These are patterns where information is encoded not only in the subset of neuron outputs that fire, but also in the order in which that subset fires. This is an interesting companion to several recent works in the neuroscience literature, showing that human memories may be stored in terms of neural spike timings. In our model, the ordering is stored in static synaptic weights using a Hebbian single-shot learning algorithm, and can be reliably recovered whenever the associated input is supplied. It is shown that the memory can operate using only unipolar binary connections throughout. The behavior of the memory under noisy input conditions is also investigated. It is shown that the memory is capable of improving the quality of the data that passes through it. That is, under appropriate conditions the output retrieved from the memory is less noisy than the input used to retrieve it. Thus, this memory architecture could be used as a component in a complex system with stable noise properties and, we argue, it can be implemented using spiking neurons     

Chiral Phosphoric Acid‐Catalyzed Enantioselective Three‐ Component Aza‐Diels–Alder Reactions of Aminopyrroles and Aminopyrazoles

A highly stereoselective three‐component Povarov reaction, catalyzed by (R)‐ and (S)‐BINOL hydrogen phosphate, was achieved for the first time with aminopyrroles and aminopyrazoles as 2‐azadiene precursors. A variety of aldehydes, enecarbamates, amino‐substituted azines participated in the reaction to afford the tetrahydropyrrolopyridines and tetrahydropyrazolopyridines in good yields with excellent diatereo‐ and enantioselectivities. A stereochemical model is proposed to account for the observed absolute stereochemistry.

     

Contribution of MRI in the evaluation of ischemic heart diseases

The high spatial and temporal resolution of MRI provides accurate identification of left ventricular endocardial and epicardial contours. Cine-MRI allows reliable and reproducible measurements of end-systolic and end-diastolic volumes, ejection fraction and left ventricular mass. These measurements are not based on any geometrical hypothesis and so remain valid in presence of ventricular deformation as observed after myocardial infarctions. The value of cine-MRI has been demonstrated in ischaemic heart disease for the study of regional left ventricular function, by analysis of left ventricular segmental function and systolic thickening of the myocardial walls. Cine-MRI may also be performed during pharmacological stress. In coronary patients without ventricular dysfunction at rest, stress cine-MRI enables detection of segmental wall motion abnormalities or reduction of systolic thickening in potentially ischaemic territories. Cine-MRI may contribute to be study of myocardial viability. Regional myocardial perfusion may also be assessed using the rapid sequences of imaging and contrast agents opacifying the intravascular compartment. In coronary patient, underperfused regions may there by be detected. The most rapid imaging techniques enable visualisation of the proximal segments of the coronary arteries and the measurement of blood velocity in the coronary arteries and the calculation of coronary reserve. Simultaneous analysis under basal conditions and after pharmacological stress of global and segmental left ventricular function and of myocardial perfusion, associated with the possibility of imaging the proximal coronary arteries and of measuring the velocity of coronary flow, makes MRI a complete non-invasive method of evaluating patients with ischaemic heart disease.     

An asynchronous ternary logic signaling system

This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.