SpecSyn: an environment supporting the specify-explore-refineparadigm for hardware/software system design

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation     

System specification with the SpecCharts language

The SpecCharts language, which builds on VHDL to meet the unique requirements of system-level specification and design, is described. With an underlying model of behavioral hierarchy, SpecCharts modeling constructs enable designers to capture system specifications simply and precisely. SpecCharts constructs facilitate system-level design tasks by permitting high-level communication, maintaining information, and allowing design modification at an easy-to-comprehend level. The results of system-level design tasks are reflected in a modified SpecCharts, enabling the designer to evaluate the quality of each step. A detailed example demonstrates the use of SpecCharts     

An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors

Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.     

Specification and design of embedded hardware-software systems

Embedded-system specification and design consists of describing a system's desired functionality and mapping that functionality for implementation by a set of system components such as processors, ASICs, memories, and buses. This paper discusses the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware synthesis, and cosimulation. The authors highlight existing tools and methods for solving those problems and describe a “specify-explore-refine” methodology for meeting today's embedded-system product development requirements     

An Introduction to High-Level Synthesis

Editor's note:High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools.—Tim Cheng, Editor in Chief     

Verification of System Level Model Transformations

This paper presents Model Algebra (MA), a formalism for representing SoC designs at system level. We define the objects and composition rules of MA and show how system level models can be represented as expressions in this formalism. The formalism is applied to a system level design methodology, where design decisions are used to gradually transform the functional specification model of the system to a transaction level model with components and communication structure. Each transformation is represented as a manipulation of a model algebraic expression, and proven for correctness using the laws of model algebra. These laws are based on the well defined execution semantics and notion of functional equivalence for MA models. Our approach promises significant savings in the verification of system level models because only the first model needs to be verified using conventional techniques. All transformations of this model, derived using MA laws, are proven to be functionally equivalent.     

Comparison of five multiprocessor systems

This paper generalizes the traditional dataflow model of computation and defines the essential problems in multiprocessing: control implementation, program partitioning, scheduling, synchronization, and memory access. The paper assumes that these essential problems are axes of a multiprocessor design space and that the solutions to these problems are values on the axes. Each point in the space represents a multiprocessor including a computational paradigm that a user must follow to achieve high performance and efficiency on the particular machine. Thus, a classification of machines from the user's point of view is introduced naturally. Five well-known multiprocessors are compared using this classification scheme.     

Associating Air Pollution with Cytokinesis-Block Micronucleus Assay Parameters in Lymphocytes of the General Population in Zagreb (Croatia)

Air pollution is recognized as one of the most serious public health issues worldwide and was declared to be a leading environmental cause of cancer deaths. At the same time, the cytokinesis-block micronucleus (CBMN) assay serves as a cancer predictive method that is extensively used in human biomonitoring for populations exposed to environmental contamination. The objective of this cross-sectional study is two-fold: to evaluate genomic instability in a sample (N = 130) of healthy, general population residents from Zagreb (Croatia), chronically exposed to different levels of air pollution, and to relate them to air pollution levels in the period from 2011 to 2015. Measured frequencies of CBMN assay parameters were in agreement with the baseline data for the general population of Croatia. Air pollution exposure was based on four factors obtained from a factor analysis of all exposure data obtained for the examined period. Based on the statistical results, we did not observe a significant positive association between any of the CBMN assay parameters tested and measured air pollution parameters for designated time windows, except for benzo(a)pyrene (B[a]P) that showed significant negative association. Our results show that measured air pollution parameters are largely below the regulatory limits, except for B[a]P, and as such, they do not affect CBMN assay parameters’ frequency. Nevertheless, as air pollution is identified as a major health threat, it is necessary to conduct prospective studies investigating the effect of air pollution on genome integrity and human health.