A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.     

On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma–Delta Modulators

This paper deals with one of the most outstanding advantages of continuous-time (CT) sigma-delta modulators compared to their discrete-time counterparts: the implicit anti-aliasing feature (AAF). Although inherent in any CT architecture, analysis of anti-aliasing properties has mostly been restricted to single-stage modulators in the past. In this contribution, extensions on analysis methods for the study of the AAF of CT multistage noise-shaping architectures are covered. A theoretical model is introduced and confirmed through simulation results. Contrary to previous belief, the results indicate that usually all stages of a cascaded architecture are involved in the anti-aliasing behaviour and hence that it is not solely determined by the first stage.     

A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.     

A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer

This paper presents a very robust 6x OSR receiver for 0.2-2 Gb/s binary NRZ signals, introducing an adaptive equalizer that is auto-calibrating on sample data statistics for reliable data recovery in presence of excessive intersymbol interference, noise and crosstalk. The proposed time domain analysis of the data eye obtained with the oversampling architecture is used to tune the equalizer transfer characteristic. The auto-calibration scheme is fully implemented in the digital domain, resulting in a hardware and power efficient architecture with low process-voltage-temperature (PVT) sensitivity. This robust and highly digitized receiver is demonstrated in 0.18 CMOS technology and is able to equalize variable cable losses up to 22 dB @ 1 GHz. The self-adaptive equalizer solution occupies only 0.05 and consumes 9 mW from a 1.8 V supply and can handle up to 20 m 100 Omega STP cable @ 2 Gb/s. The entire receiver consumes 110 mW operating at 2 Gb/s with bit error rates of better than < 10^-12.