排序方式: 共有27条查询结果,搜索用时 15 毫秒
1.
Aloisi W. Giustolisi G. Palumbo G. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(2):77-84
This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided. 相似文献
2.
O. Giustolisi 《Canadian Metallurgical Quarterly》2010,136(11):889-900
The classical assumption of representing total demand along a pipe as two lumped withdrawals at its terminal nodes is hitherto common. It is a simplification of the network topology which is useful in order to drastically reduce the number of nodes during network simulation. Conversely, this simplification does not preserve energy balance equation of pipes and, for this reason, it is an approximation that could generate significant head loss errors. This paper presents a modification of the global gradient algorithm (GGA) which entails an enhancing of GGA (EGGA) permitting the effective introduction of the lumped nodal demands, without forfeiting correctness of energy balance, by means of a pipe hydraulic resistance correction. The robustness and convergence properties of the algorithm are compared with those of the classical GGA. Furthermore, the effectiveness of EGGA is demonstrated by computing the network pressure status under different configurations of the connections along the pipes of a test network. 相似文献
3.
A new block for the implementation of the function is presented. It is based on structures commonly used in SC circuits and is fully compatible with this approach. The circuit was realised in a 1.2 μm standard CMOS technology. The experimental results show good agreement with the predicted results 相似文献
4.
A CMOS low-voltage output stage based on a push-pull topology is proposed. It is driven by a differential signal and its symmetric topology provides excellent intrinsic linearity. It can work with a power supply as low as 1 V and when loaded with a 500 /spl Omega/ resistor it exhibits negligible even harmonic components whilst odd components are maintained well below -20 dB up to 900 mV/sub pp/ of the output signal. Moreover, the output stage includes a simple current control which accurately sets the bias condition. 相似文献
5.
G. Giustolisi G. Palmisano G. Palumbo 《International Journal of Circuit Theory and Applications》2001,29(3):321-330
A novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil‐and‐paper optimized design procedure and a detailed analysis of second‐order non‐idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 µm CMOS process setting a 3 V power supply and simulations have been performed to validate results. Copyright © 2001 John Wiley & Sons, Ltd. 相似文献
6.
Design guidelines of CMOS class-AB output stages: a tutorial 总被引:1,自引:0,他引:1
Walter Aloisi Giuseppe Di Cataldo Gianluca Giustolisi Gaetano Palumbo 《Analog Integrated Circuits and Signal Processing》2008,56(3):163-177
This article presents useful guidelines for designing CMOS class-AB output stages. Three Quality Factors, which allow analysis and comparison of different output stages, are used to design two CMOS class-AB stages. We show that using the proposed Quality Factors and the related strategy leads to an efficient design in terms trade-off among area, current consumption, bandwidth and distortion. Indeed, for one of the two stages adopted as example, the design through the Quality Factors results in superior distortion performance with respect to the design suggested in the original article. Design examples and simulations are provided to validate the design strategy. 相似文献
7.
1.5 V power supply CMOS voltage squarer 总被引:3,自引:0,他引:3
A CMOS voltage squarer for low voltage applications is proposed. The circuit works with a 1.5 V power supply and provides a THD of <3% with input signals up to 260 mVpp. A 0.3% lower THD is achieved with input signals up to 120 mVpp 相似文献
8.
Increasingly, water loss via leakage is acknowledged as one of the main challenges facing water distribution system operations. The consideration of water loss over time, as systems age, physical networks grow, and consumption patterns mature, should form an integral part of effective asset management, rendering any simulation model capable of quantifying pressure-driven leakage indispensable. To this end, a novel steady-state network simulation model that fully integrates into a classical hydraulic representation, pressure-driven demand and leakage at the pipe level is developed and presented here. After presenting a brief literature review about leakage modeling, the importance of a more realistic simulation model allowing for leakage analysis is demonstrated. The algorithm is then tested from a numerical standpoint and subjected to a convergence analysis. These analyses are performed on a case study involving two networks derived from real systems. Experimentally observed convergence/error statistics demonstrate the high robustness of the proposed pressure-driven demand and leakage simulation model. 相似文献
9.
Angelo Doglioni Francesca Primativo Daniele Laucelli Valeria Monno Soon-Thiam Khu Orazio Giustolisi 《Environmental Modelling & Software》2009,24(12):1522-1528
The simulation of sewage systems and wastewater treatment plants is strategic for assessing the effect of new dwellings on the existing water facilities. This paper introduces an integrated framework made by a land use change model, a sewage system simulator, and a wastewater treatment plant simulator. This is a complex system since each element is characterized by different dynamics. The land use change model simulates the annual expansion of an urban area according to planners’ guidelines; the sewage system simulator investigates the response of the drainage system to the expansion. The wastewater treatment plant is simulated in order to assess the impact of the new outflows on the existing plant. The three models are integrated into a Simulink model. Two components of the developed framework are based on models well established in literature. The proposed framework is tested on a simple case study of a small town located in south west of Scotland. 相似文献
10.
Water Resources Management - Water losses in urban water distribution networks (WDN) accelerate the deterioration of such infrastructures. The enhanced hydraulic modelling provides a... 相似文献