Experimental real-time detector of GSM terminals

The authors present an experimental real-time GSM terminal detector, to be installed in a restricted area. The detector triggers terminal signaling, which can be captured.     

Real-time 3G UMTS terminal detection

The authors study the feasibility of a real-time 3G UMTS terminal detector to be located in a restricted area. All idle terminals entering the restricted area are forced to emit signaling information which can be captured. The authors analyze the detector protocol settings and response time. They also determine the conditions it would impose on UMTS operators     

Real-time detector of GSM terminals

The authors propose a feasible real-time GSM terminal detector, to be located in a restricted area. All idle terminals entering it are forced to emit signaling information, which can be captured. As far as the authors know, market alternatives are nonexistent. A possible application is presented: a mobile terminal detector for airport access bridges     

Neural parallel-hierarchical-matching scheduler for input-bufferedpacket switches

Input-buffered packet switches boosted with high-performance schedulers achieve near-100% throughput. Several authors have proposed the use of neural schedulers. These schedulers have a fast theoretical convergence, but the standard deviation of the number of iterations required can be arbitrarily large. In a previous paper, the authors proposed a hybrid digital-neural scheduler, HBRTNS, with bounded response time: O(N) clock steps. As an evolution of that concept, the authors present a two-stage neural Parallel-Hierarchical-Matching scheduler (nPHM), which generates high quality solutions in few clock steps. We present numerical comparisons with diverse state-of-the-art algorithms and the ideal output-buffered case     

High performance real-time neural scheduler for ATM switches

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time     

Real-time interception systems for the GSM protocol

A GSM protocol interceptor is a device located in a (possibly) closed area that listens to information exchanged between base stations (BSs) and mobile stations (MSs). This paper presents three new interception systems for security purposes. The first one (detector) forces all idle MSs nearby to generate activity, which can be used to activate an alarm of MS presence. The second one (selective interceptor) monitors information exchange between MS and BS and, in case of MS activity, (1) extracts messages containing MS identifiers and (2) checks identifiers in a local cache to decide if an external jamming unit should block individual calls (either incoming or outgoing). The third system (enhanced selective interceptor) combines the previous two systems to improve blocking performance. We analyze transactions of the GSM protocol that are relevant to interception system operation. Those transactions impose real-time constraints that we quantify. We present real tests and simulations that address the feasibility of the systems.     

On the behavior of PHM distributed schedulers for input buffered packet switches

iSLIP and parallel hierarchical matching (PHM) are distributed maximal size matching schedulers for input-buffered switches. Previous research has analyzed the hardware cost of those schedulers and their performance after a small number of iterations. In this paper, we formulate an upper bound for the number of iterations required by PHM to converge. Then, we compare the number of iterations required by iSLIP and PHM to achieve a maximal throughput under uniform Bernoulli traffic, by means of simulation. Finally, we obtain the corresponding delay performances, which are similar. The results suggest that PHM has both the advantages of previous hierarchical matching algorithms (low hardware complexity) and iSLIP (low number of iterations).     

Fast image recovery using dynamic load balancing in parallelarchitectures, by means of incomplete projections

This paper formulates an incomplete projection algorithm that is applied to the image recovery problem. The algorithm allows an easy implementation of dynamic load balancing for parallel architectures. Furthermore, the local computation-communication load ratio can be adjusted, since each processor performs a finite number of iterations of any projection-type technique, and this number can be provided as a parameter of the algorithm. Numerical results compare favorably with those obtained by the extrapolated method of parallel subgradient projections.