A reconfigurable 8 GOP ASIC architecture for high-speed datacommunications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose flexibility. The proposed architecture can he used to realize any one of several functional blocks needed for the physical layer implementation of data communication systems operating at symbol rates in excess of 125 Msymbols/s. Multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions): real and complex FIR/IIR filtering, least mean square (LMS)-based adaptive filtering, discrete Fourier transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 125 Msamples/s. All of the modes are mapped onto a common, regular data path with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks     

Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal

The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-mum 1.8-V CMOS technology and requires a total area of 72mm² consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals     

Simulation,implementation and performance evaluation of a diversity enabled WCDMA mobile terminal

Smart antenna array technology has been shown to greatly improve the performance of wireless communication systems. In this article, we describe the impact of smart antenna array processing at the mobile terminal for Wideband Code Division Multiple Access (WCDMA) cellular networks. Using system simulations we demonstrate the quality of service, network coverage, and network capacity improvement provided by a WCDMA dual antenna receiver and we establish a relationship between this improvement and the link level performance. We then describe a receiver architecture for a dual antenna WCDMA mobile receiver. The proposed receiver was implemented, as part of a complete mobile terminal solution, in an ASIC using a 0.18 μm, 1.8 V CMOS technology. The ASIC was integrated with RF, analog and digital components in a PCMCIA card form factor. The PCMCIA is a 3GPP compliant user equipment and has been submitted to standardized performance and conformance tests. Experimental measurements gathered with the PCMCIA card illustrate the impact of a diversity enabled mobile data terminal on the link level performance. For various propagation environments and transmission data rates, improvements in the range of 2.7 – 10 dB in the required DPCH I _c/I _or for a 1% Block Error Rate (BLER) were observed. These measurements are within 1.4 dB of the ideal link level simulations which indicates that the predicted improvement at the network level should also materialize. The results presented in this paper show the tremendous potential of smart antenna arrays in 3G WCDMA cellular networks and establish diversity as a viable solution for high-speed cellular communications.     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

Design and VLSI implementation for a WCDMA multipath searcher

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 /spl mu/m CMOS technology and requires only 150 k gates for a total area of 1.5 mm/sup 2/ consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.