TRANSPORT PHENOMENA IN MICRO HEAT EXCHANGERS WITH CORRUGATED WALLS

Heat exchangers with corrugated walls are well known as macro heat exchangers. In previous systematic analyses heat exchangers with crosswise corrugated walls at large Reynolds numbers were analyzed. The wall corrugation was generated by sinusoidally shaped walls as well as by crosswise corrugated cylinders of different cross sections on plane walls, such as those being used as spacers in membrane technology. The low-Reynolds-number range of these structures is also interesting for application as micro heat exchangers. Therefore first results will be presented, where such structures are experimentally analyzed in the low-Reynolds-number range up to Re S 10, especially interesting for applications as micro heat exchangers. For the use of corrugated walls in the free-flow arrangement, first new results at low Reynolds numbers for this heat exchanger geometry are presented, where the transition from turbulent to laminar flow range is dominated by the Görtler-Dean instability.     

The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor

As CMOS feature sizes continue to shrink and traditional microarchitectural methods for delivering high performance (e.g., deep pipelining) become too expensive and power-hungry, chip multiprocessors (CMPs) become an exciting new direction by which system designers can deliver increased performance. Exploiting parallelism in such designs is the key to high performance, and we find that parallelism must be exploited at multiple levels of the system: the thread-level parallelism that has become popular in many designs fails to exploit all the levels of available parallelism in many workloads for CMP systems. We describe the Cell Broadband Engine and the multiple levels at which its architecture exploits parallelism: data-level, instruction-level, thread-level, memory-level, and compute-transfer parallelism. By taking advantage of opportunities at all levels of the system, this CMP revolutionizes parallel architectures to deliver previously unattained levels of single chip performance. We describe how the heterogeneous cores allow to achieve this performance by parallelizing and offloading computation intensive application code onto the Synergistic Processor Element (SPE) cores using a heterogeneous thread model with SPEs. We also give an example of scheduling code to be memory latency tolerant using software pipelining techniques in the SPE. This paper is based in part on “Chip multiprocessing and the Cell Broadband Engine”, ACM Computing Frontiers 2006.     

Dynamic and transparent binary translation

High-frequency design and instruction-level parallelism (ILP) are important for high-performance microprocessor implementations. The Binary-translation Optimized Architecture (BOA), an implementation of the IBM PowerPC family, combines binary translation with dynamic optimization. The authors use these techniques to simplify the hardware by bridging a semantic gap between the PowerPC's reduced instruction set and even simpler hardware primitives. Processors like the Pentium Pro and Power4 have tried to achieve high frequency and ILP by implementing a cracking scheme in hardware: an instruction decoder in the pipeline generates multiple micro-operations that can then be scheduled out of order. BOA relies on an alternative software approach to decompose complex operations and to generate schedules, and thus offers significant advantages over purely static compilation approaches. This article explains BOA's translation strategy, detailing system issues and architecture implementation     

Josephson junctions with 1 ?m dimensions and with picosecond switching times

Josephson junctions with 1 × 3 ?m dimensions have no resonances. For a current density of about 1000 A/cm2, the risetime of the switching transient from zero to the gap voltage is below 38 ps.