Generic Description and Synthesis of LDPC Decoders

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.     

PAPR reduction for LDPC coded OFDM systems using binary masks and optimal LLR estimation

A probabilistic PAPR reduction method using binary masks is proposed for OFDM systems. The binary masks are used to generate multiple signal candidates containing the same information. The candidate with the lowest PAPR is selected for transmission. In the presence of a non-linear amplifier (soft limiter), as the number of candidates increases, the PAPR is reduced, resulting in the reduction of clipping distortion power. Taking into account both distortion and channel noise, we derive the analytical total noise power to estimate the log-likelihood ratio (LLR), which is then used to enhance the decoding performance. We derive a minimum achievable E_b/N₀ and a decoding threshold for LDPC codes in the presence of the soft limiter. Simulation results show that our LLR estimation improves the error performance, and multiple candidate system lowers the error rate.