Chemical Approach to Biological Safety: Molecular‐Level Control of an Integrated Zinc Finger Nuclease

Application of artificial nucleases (ANs) in genome editing is still hindered by their cytotoxicity related to off‐target cleavages. This problem can be targeted by regulation of the nuclease domain. Here, we provide an experimental survey of computationally designed integrated zinc finger nucleases, constructed by linking the inactivated catalytic centre and the allosteric activator sequence of the colicin E7 nuclease domain to the two opposite termini of a zinc finger array. DNA specificity and metal binding were confirmed by electrophoretic mobility shift assays, synchrotron radiation circular dichroism spectroscopy, and nano‐electrospray ionisation mass spectrometry. In situ intramolecular activation of the nuclease domain was observed, resulting in specific cleavage of DNA with moderate activity. This study represents a new approach to AN design through integrated nucleases consisting of three (regulator, DNA‐binding, and nuclease) units, rather than simple chimera. The optimisation of such ANs could lead to safe gene editing enzymes.     

Cardiorespiratory and electrolytic changes in status asthmaticus after intravenous administration of magnesium sulfate

The authors studied cardiorespiratory effects of MgSO4 infusion in 30 randomized patients with status asthmaticus. They found, that after having the drug administered, values of VC, FEV1, FIV1, PaO2 and pH increased, the respiratory and heart rate, diastolic blood pressure reduced. Other ventilation, blood gas and ECG parameters were unchanged. Among the electrolytes, serum Ca2+ level has reduced, both plasma and intracellular Mg2+ concentrations increased. It is apparent from the results, that broncholytical ability of MgSO4 given in therapeutical dose i.v. does not reach the level of beta-stimulating agents. However, this completed with the cardioprotective, sedative effect as well as more advantageous ion-distribution, influences favourably the asthmatic dyspnoea.     

A global model for rapid thermal processors

A simple model for the components that make up a rapid thermal processing system is given. These components are the furnace, the pyrometer used to measure temperature, and the control system that utilizes the pyrometer measurement to control the power to the lamps. The models for each of the components are integrated in a numerical code to give a computer simulation of the complete furnace operation. The simulation can be used to investigate the interaction of the furnace, temperature-sensing technique, and the control system. Therefore, the interplay of heat transfer (furnace) properties, optical (pyrometer) parameters, and control gains can be studied. The objective is to define variability in wafer temperature as process parameters change. The following three applications of the model are included: (1) a simulation of open-loop operation; (2) a simulation of the ramp up and subsequent operation with a step change in wafer optical properties; and (3) a simulation of the rapid thermal chemical vapor deposition of polysilicon on silicon oxide which demonstrates the applicability model for actual processes. A technique for correction of pyrometer output to improve temperature control is also presented     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Single-wafer cluster tool performance: an analysis of the effectsof redundant chambers and revisitation sequences on throughput

Recent trends in the semiconductor industry indicate the need to explore alternatives to batch-wafer manufacturing. One proposed alternative is a micro-factory based on cluster tools. This paper presents an analysis of the effect of redundant chambers and chamber revisitation process sequences on the throughput in an individual cluster tool. Theoretical models which quantify the time required to process a lot of wafers in a cluster tool are developed for these situations. The differences between scheduling algorithms which use the load-lock as a queue and those that do not are also explored. Finally, the models developed in the work are integrated into a model which bounds the minimum theoretical turn-around-time which can be achieved in a cluster based fab     

Toward a general-purpose analog VLSI neural network with on-chiplearning

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.     

An analog VLSI neural network with on-chip perturbation learning

An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, high-volume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K μm² in a 2-μm technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in ten's of milliseconds and 4-b parity in hundred's of milliseconds     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

Thermal uniformity and stress minimization during rapid thermalprocesses

The practical development and implementation of rapid thermal processes will significantly influence the semiconductor fabrication industry. With the capability to perform heat cycles quickly and with low thermal budgets, rapid thermal processors have the potential to supplant conventional thermal systems in the years to come. Currently, rapid thermal processors are unable to match the thermal process uniformity produced in conventional convective-based systems. Using a thermal model to approximate the heating characteristics of silicon wafers, it is possible to determine the effects of time-varying intensity profiles on a wafer during a rapid thermal process. Interpretation of this model shows idealized intensity profiles can maintain thermal uniformity at steady-state temperatures. During thermal transients a dynamic continuously changing profile is required to maintain thermal uniformity. As a predictive tool, this analysis can be used to determine and evaluate dynamic uniformity producing intensity profiles before thermal transients occur within a process. This approach can reduce the accumulation of error during high temperature steps not only by providing thermal uniformity at steady states, but by reducing the initial nonuniformities produced by transitions. This paper will review the wafer model, show the results of an idealized profile for steady-state and transient temperatures, and explain the dynamic profiles required for continuous uniformity     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system