Novel edge suppression technique for planar avalanche photodiodes

We present an advanced drift diffusion simulation of the joint opening effect (JOE) avalanche photodiode (APD). The joint opening effect APD is a new design for achieving edge breakdown suppression in planar avalanche photodiodes. It is a single growth process that achieves center breakdown dominance without the use of guard rings, partial charge sheets, or surface etches. The JOE APD only requires the diffusion of the primary well. Edge breakdown suppression is achieved by partially insulating the electric field growth in the active region from the geometry of the primary well     

Numerical simulation of avalanche breakdown within InP-InGaAs SAGCMstandoff avalanche photodiodes

The breakdown location within a planar InP/In_0.53Ga_0.47As (InGaAs) separate absorption, grading, charge sheet, and multiplication (SAGCM) avalanche photodiode (APD), using the standoff breakdown suppression design to replace guard rings, depends on the two-dimensional (2-D) geometry of the Zn diffused well. Since the geometry of this p⁺ diffusion is dependent upon the surface etch, the effects of varying the etch depth (t_standoff) and length of the sloped etch edge (w_slope ) are studied using a two-dimensional drift-diffusion simulator. It is determined that the etch depth brackets a region where center breakdown dominance is possible. To ensure center breakdown within this region it is concluded that there is a maximum value that the slope of the etch walls must not exceed     

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.     

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 /spl mu//spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f/sub T//f/sub MAX/ values of 41/42 GHz were demonstrated for 0.5/spl times/10/spl mu/m/sup 2/ transistors.