C-trust: A trust management system to improve fairness on circular P2P networks

An important issue in Peer-to-Peer networks is to encourage users to share with others as they use the resources of the network. However, some nodes may only consume from users without giving anything in return. To fix this problem, we can incorporate trust management systems with network infrastructures. Current trust managements are usually made for unstructured overlays and have several shortcomings. They are made to be very similar to e-commerce scoring websites which may not be the best design for fairness in P2P networks. Several problems may arise with their designs such as difficulties to provide a complete history of freeloaders or lack of an autonomous removal mechanism in case of severe attacks. In this paper, we argue that such systems can be deployed more efficiently by using a structured paradigm. For this purpose, we propose C-Trust, a trust management system which is focused on fairness for P2P networks. This is done by getting help from current circular structured designs. This method is able to mark freeloaders, identify their severity of abusion and punish them accordingly. We are also able to effectively protect both Seeder-to-Leecher and Leecher-to-Leecher transactions. This feature is specially important for fairness which other trust systems have not considered so far.     

Design Considerations for a Real-Time Ocular Counterroll Instrument

A video-based technique for measuring the torsional movement of the eye (counterroll) by processing video images of the eyeball is presented. Spectral estimates show that most of the variance of the iris image is in the angular direction. It will be demonstrated that cross correlation between sequences that are obtained by circular sampling of the digitized image of the iris is sufficient to extract the counterroll information. Computation time for angular correlation is thus significantly reduced and real-time hardware implementation becomes feasible. As the result of a preprocessing step, we obtain the information about the horizontal and vertical movement of the eye and also the diameter of the pupil. To improve the measurement resolution, a fast second degree local least square interpolation of the cross-correlation function is used. Possible sources of error and the limitations of the algorithm will be studied. The results of the computer simulations made using the algorithm serve to experimentally confirm the error estimates. Application of the algorithm to photographically obtained image data from human subjects demonstrates its practicality on normal eyes. The system design for a device for measuring 3D movement of the eye will be discussed.     

In vivo and in vitro evaluation of the wound healing properties of chitosan extracted from Trametes versicolor

Journal of Polymer Research - Three chitosan-derived compounds, Ch-I, Ch-Qn, and Ch-TPA, were synthesized through condensation reactions between high-molecular weight chitosan and three different...     

A 200 MHz CMOS broad-band switching chip

The architecture of a 32-channel, 200 MHz Batcher-Banyan fabric chip for broadband ATM packet switching is described, as well as the design methods required to develop a 380 K-transistor CMOS device that operates at these speeds under worst-case conditions. This device routes packets from 32 sources to any 32 destinations, is completely reconfigured each packet period, maintains priorities, supports contention resolution, and is a building block for larger switches     

An 85-MHz fourth-order programmable IIR digital filter chip

The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10×10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm². It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5×10⁹ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed