Efficient Management of Persistent Knowledge

Although computer speed has steadily increased and memory is getting cheaper, the need for storage managers to deal efficiently with applications that cannot be held into main memory is vital. Dealing with large quantities of clauses implies the use of persistent knowledge and thus, indexing methods are essential to access efficiently the subset of clauses relevant to answering a query. We introduce PerKMan, a storage manager that uses G-trees, and aims at efficient manipulation of large amounts of persistent knowledge. PerKMan may be connected to Prolog systems that offer an external C language interface. As well as the fact that the storage manager allows different arguments of a predicate to share a common index dimension in a novel manner, it indexes rules and facts in the same manner. PerKMan handles compound terms efficiently and its data structures adapt their shape to large dynamic volumes of clauses, no matter what the distribution. The storage manager achieves fast clause retrieval and reasonable use of disk space.     

Supply current testing in linear bipolar ICs

Fault detection in linear bipolar integrated circuits using power supply current measurements is investigated. The most prevalent, catastrophic and parametric faults, have been modelled for a representative (741 type) opamp. The circuit is simulated under both linear and nonlinear operation. Comparative results between power supply current and output voltage measurements are given, showing the improvement in fault coverage by the use of the current sensing method.<>     

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.     

An analytical hot-carrier induced degradation model in polysilicon TFTs

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.     

RF sputtered indium-tin-oxide as antireflective coating for GaAs solar cells

Conductive and antireflective indium-tin-oxide (ITO) has been prepared by RF sputtering in Ar atmosphere, without introducing oxygen into the plasma and on room temperature substrates in order to be used as antireflective coating on GaAs solar cells. The electrical resistivity of the n-type, degenerate ITO films exhibited a reduction with deposition rate and an increase with total pressure, while it was independent of the film thickness in the range of 20 nm to 130 run. Further reduction of resistivity, up to 4 × 10⁻⁴ Ωcm, was obtained by annealing at 400°C. This is the lowest resistivity that has been reported for TTO films prepared under similar conditions. The transmittance of 90 nm thick ITO film was 85% and the reflectance of p/n GaAs solar cell was reduced from 35% to 2% after the ITO layer application.     

Reducing the number of nonzero elements of topological loop (B) and cutset (D) matrices

Topological loop (B) and cutset (D) matrices are used to formulate systems of equations in many applications in symbolic network analysis and fault diagnosis of electronic circuits. The minimisation of the number of their nonzero elements leads to more effective manipulation of the resulting equations. A simple and efficient algorithm for the reduction of the number of these nonzero elements is introduced and some applications are presented showing its effectiveness.<>     

Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog

Nowadays, the semiconductor industry directs its attention to mixed-signal System-on-Chip (SoC) applications. Main targets are the creation of accurate and fast mixed-signal SoC designs, composed of both digital and analog components, and the reduction of time to market for this kind of integrated circuits (ICs). In order to bring a mixed-signal SoC faster to the market, higher system-level simulation speed is required, with respect to traditional modeling approaches. Real Number Modelling (RNM) could be an effective solution. In this work, a sigma-delta analog-to-digital converter (ADC), a voltage-controlled oscillator (VCO) and a digital phase-locked loop (PLL) are implemented as real number models using SystemVerilog. This paper is an extended version of work previously published by the authors. Herein, more accurate and parameterizable models were created, while their validation process is analyzed and achieved using a novel metric for accuracy estimation. The proposed models’ parameterizability enhances the usability of the models to various SoC designs. Aim of this work is to underline the RNM effectiveness provided by SystemVerilog, and exhibit a way to apply RNM for modeling and simulation of widely used analog/mixed-signal (AMS) blocks. The presented real number models were compared to Verilog-A, Verilog-AMS, and transistor-level SPICE models. All tests showed that the proposed real number models based on SystemVerilog demonstrate noteworthy improvement on simulation efficiency, with respect to previous works in the literature, preserving simultaneously sufficient accuracy.