Optimized test circuits for SER characterization of a manufacturingprocess

Novel test circuits for the accurate determination of soft error rate (SER) dependency on critical charges Q_CRIT have been developed. The minimum charge necessary for flipping the state of a sensor cell, denoted by Q_CRIT, is measured with 1%-2% accuracy before exposing the circuits to radiation. During the accelerated testing, circuits biased with multiple different supply voltages V_CC are simultaneously placed into a beam and any bit flips are logged. From the measured SER dependency on V_CC and previously measured Q_CRIT dependency on V_CC, the dependency of SER on Q_CRIT can be deduced by correlating V_CC's for the two measurements. Furthermore, the sensor cell utilizes a single dynamic node which can be programmed to detect strikes on either N- or P-type diffusions, but not both at the same time. The measured dependency SER(Q_CRIT), normalized by the diffusion area, can be used for predicting SER of any other circuit fabricated in the same process and aid designers in optimization for reduced SER. Predictions of a theoretical SER model, if one is available, can be compared directly with the measurements. Since the true Q_CRIT of the test circuits is known accurately, any discrepancy larger than given by the measurement uncertainty of SER(Q_CRIT) would be clearly due to limitations of the SER model. We implemented the test circuits in a 0.6-μm bulk CMOS process and verified accuracy of Q_CRIT(V_CC) calibration method     

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

Nociceptive mechanisms modulate ozone-induced human lung function decrements

We have previously suggested that ozone (O3)-induced pain-related symptoms and inhibition of maximal inspiration are due to stimulation of airway C fibers (M. J. Hazucha, D. V. Bates, and P. A. Bromberg. J. Appl. Physiol. 67: 1535-1541, 1989). If this were so, pain suppression or inhibition by opioid-receptor agonists should partially or fully reverse O3-induced symptomatic and lung functional responses. The objectives of this study were to determine whether O3-induced pain limits maximal inspiration and whether endogenous opioids contribute to modulation of the effects of inhaled O3 on lung function. The participants in this double-blind crossover study were healthy volunteers (18-59 yr) known to be "weak" (WR; n = 20) and "strong" O3 responders (SR; n = 42). They underwent either two 2-h exposures to air or two 2-h exposures to 0. 42 parts/million O3 with moderate intermittent exercise. Immediately after post-O3 spirometry, the WR were randomly given either naloxone (0.15 mg/kg iv) or saline, whereas SR randomly received either sufentanil (0.2 microgram/kg iv) or saline. O3 exposure significantly (P < 0.001) impaired lung function. In SR, sufentanil rapidly, although not completely, reversed both the chest pain and spirometric effects (forced expiratory volume in 1 s; P < 0.0001) compared with saline. Immediate postexposure administration of saline or naloxone had no significant effect on WR. Plasma beta-endorphin levels were not related to an individual's O3 responsiveness. Cutaneous pain variables showed a nonsignificant weak association with O3 responsiveness. These observations demonstrate that nociceptive mechanisms play a key role in modulating O3-induced inhibition of inspiration but not in causing lack of spirometric response to O3 exposure in WR.     

Characterization of soft errors caused by single event upsets in CMOS processes

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.     

High-voltage power delivery through charge recycling

In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC-DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18-/spl mu/m CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.     

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm² for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work     

Area-efficient linear regulator with ultra-fast load regulation

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.     

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction

The impedance of a microprocessor power-delivery network peaks at ~140 MHz, resulting in power-grid resonance, which lowers operating frequency and compromises gate oxide integrity. A suppression circuit is designed using an active-damping technique with a maximum of 13 dB supply voltage noise reduction from 70 to 250 MHz in a 90 nm CMOS process.     

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.     

An aerosol generator system for inhalation delivery of pharmacologic agents

Most commercially available aerosol generators widely used in medical applications produce aerosols characterized by a large mass median diameter in the 4-8 micron range and the particle size in the 0.1-10.0 microns range. The desirable size of therapeutic and diagnostic aerosols, however, is about 2-4 microns mass median diameter, and less than 2.0 geometric standard deviation; this size increases the reproducibility of inhalation tests and enhances drug efficacy. We combined the commercially available DeVilbiss Model 65 nebulizer with a dilution/mixing chamber developed in our laboratory. The characteristics of this aerosol generator system were examined over a range of operating conditions and concentrations of solutions of three bronchoconstrictive agents--histamine, carbachol, and methacholine. The aerosol generator system produced a polydispersed aerosol with a mass median diameter range of 1.7-2.4 microns and geometric standard deviation of 1.5. The reliable and reproducible operation of the aerosol generator system greatly increases the power of bronchial challenge tests with bronchoconstrictive drugs.