A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

Effect of coupled dissolution and redox reactions on Cr(VI)aq attenuation during transport in the sediments under hyperalkaline conditions

Aluminum-rich, hyperalkaline (pH > 13.5) and saline high-level nuclear waste (HLW) fluids at elevated temperatures (>50 degrees C), that possibly contained as much as 0.41 mol L(-1) Cr(VI), accidentally leaked to the sediments at the Hanford Site, WA. These extreme conditions promote base-induced dissolution of soil minerals which may affect Cr(VI)aq mobility. Our objective was to investigate Cr(VI)aq transport in sediments leached with HLW simulants at 50 degrees C, under CO2 and O2 free conditions. Results demonstrated that Cr(VI)aq fate was closely related to dissolution, and Cr(VI)aq mass loss was negligible in the first pore volumes but increased significantly thereafter. Similar to dissolution, Cr(VI)aq attenuation increased with increasing fluid residence time and NaOH concentration but decreased with Al concentrations in the leaching solutions. Aqueous Cr(VI) removal rate half-lives varied from 1.2 to 230 h with the fastest at the highest base concentration, lowest Al concentration, greatest reaction time, and lowest Cr(VI) concentration in the leaching solution. The rate of Cr(VI) removal (normalized to 1 kg of solution) varied from 0.83 x 10(-9) (+/-0.44 x 10(-9)) to 9.16 x 10(-9) (+/-1.10 x 10(-9)) mol s(-1). The predominant mechanism responsible for removing Cr(VI) from the aqueous phase appears to be homogeneous Cr(VI) reduction to Cr(III) by Fe(II) released during mineral dissolution. Cr(VI)aq removal was time-limited probably because it was controlled by the rate of Fe(II) release into the soil solution upon mineral dissolution, which was also a time-limited process, and other processes that may act to lower Fe(II)aq activity.     

Sediment transport over a flat bed in a unidirectional flow: simulations and validation

A discrete particle model is described which simulates bedload transport over a flat bed of a unimodal mixed-sized distribution of particles. Simple physical rules are applied to large numbers of discrete sediment grains moving within a unidirectional flow. The modelling assumptions and main algorithms of the bedload transport model are presented and discussed. Sediment particles are represented by smooth spheres, which move under the drag forces of a simulated fluid flow. Bedload mass-transport rates calculated by the model exhibit a low sensitivity to chosen model parameters. Comparisons of the calculated mass-transport rates with well-established empirical relationships are good, strongly suggesting that the discrete particle model has captured the essential elements of the system physics. This performance provides strong justification for future interrogation of the model to investigate details of the small-scale constituent processes which have hitherto been outside the reach of previous experimental and modelling investigations.     

A third-generation SPARC V9 64-b microprocessor

This quad-issue processor achieves 1-GHz operation through improved dynamic circuit techniques in critical paths and a more extensive on-chip memory system which scales in both bandwidth and latency. Critical logic paths use domino, delayed clocked domino, and logic embedded in dynamic flip-flops for minimum delay. A 64-KB sum-addressed memory data cache combines the address offset add with the cache decode, allowing the average memory latency to scale by more than the clock ratio. Memory bandwidth is improved by using wave pipelined SRAM designs for on-chip caches and a write cache for store traffic. Memory power is controlled without increased latency by use of delayed-reset logic decoders. The chip operates at 1000 MHz and dissipates less than 80 W from a 1.6-V supply. It contains 23 million transistors (12 million in RAM cells) on a 244 mm² die     

A new family of semidynamic and dynamic flip-flops with embeddedlogic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well