Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

新一代NV SRAM技术

第一代NV SRAM模块问世近20年来，NVSRAM技术不断更新，以保持与各种应用同步发展，同时满足新的封装技术不断增长的需求。     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Brain lateralization and severity of stuttering in children

Cerebral lateralization in visual perception was investigated in 9 severe stuttering, 11 mild stuttering and 48 fluent speakers. The subjects were asked to identify words presented in the left or right visual field for 20 ms. Children responded by pointing to the exposed test word on a response card which contained four different words. Errors committed in the left and right visual fields were analyzed. The data showed a left hemisphere superiority in the processing of words in both the mild stutterers and the fluent speakers, but a right hemisphere advantage in the severe stutterers. The results suggest a close relationship between the severity of stuttering and functional brain organization.     

On the hot-carrier-induced post-stress interface trap generation inn-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D_it-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior     

Empirically derived subtypes of adolescent depression: Latent profile analysis of co-occurring symptoms in the Treatment for Adolescents with Depression Study (TADS).

A latent profile analysis was conducted on the co-occurring symptoms of 423 adolescents diagnosed with major depressive disorder as part of the Treatment for Adolescents with Depression Study (TADS), a multisite, randomized treatment trial. The participants had a mean (SD) age of 14.6 (1.5) years; of the sample, 45.6% was male and 73.8% was white. Scores on the primary subscales of Conners' Parent Rating Scale-Revised were used as indicators in the analysis. Five classes of symptoms best described the clinical presentation of adolescents enrolled in the TADS. Of the adolescents in the sample, 80% were assigned to classes with clinically significant elevations on 1 or more subscales of the Children's Depression Rating Scale-Revised. The 5 classes met empirical criteria for distinctiveness and were validated against clinical diagnoses, child-rated symptoms, and clinician-rated functional impairment. The findings are consistent with prior studies that showed a high rate of co-occurring symptoms among depressed adolescents. The discussion focuses on understanding subtypes and comorbidity in adolescent depression as well as the implications for treatment and for prevention. (PsycINFO Database Record (c) 2010 APA, all rights reserved)